Pierre Tomasini

Are Si/SiGe Tunneling Field-Effect Transistors a Good Idea?

Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn-off mechanism in MOSFETs forces a fundamental trade-off between leakage power and performance when the voltage is reduced. Tunneling field effect transistors (TFETs) could overcome this limitation since these devices have been theoretically shown to be capable of subthreshold slopes < 60 mV/decade [1]. However, the band gap of silicon (1.12 eV) is too large to provide acceptable drive currents in Si-based TFETs. TFETs fabricated using Si/SiGe heterojunctions [2] have the potential for increased drive current since the type-II band alignment reduces the effective band gap for tunneling at the source electrode. In this talk, I will show experimental results on Si/SiGe heterojunction tunneling transistors (HETTs), along with quantum transport simulations on a variety of heterojunction TFET geometries, and then describe the implications of these results on the viability of the Si/SiGe material system for TFET fabrication. Si/SiGe HETTs. The devices were fabricated using a conventional CMOS process flow that was modified to allow the source and drain electrodes to be formed in separate processing steps. The devices utilized SOI starting substrates and a high-κ/poly gate stack. The n drain was formed by conventional As implantation and anneal, while the source electrode was formed by selective etching of Si underneath the gate electrode and regrowth of in-situ-doped p Si1-xGex. Typical Id vs. Vgs characteristics at room temperature for HETTs with source Ge concentrations of 7% and 25% are shown in Fig. 2 [3]. The improved performance for the devices with x = 25% over x = 7% provides a clear indication of the heterojunction benefit on TFET performance. However, the devices fall short of achieving sub-60 mV/dec subthreshold slopes or the necessary drive currents for practical applications. Broken-gap TFETs. In order to further explore the heterojunction band structure requirements for TFETs, quantum transport simulations are performance on a variety of HETTs with band alignment ranging from staggered to broken gap [4]. The results, shown in Fig.3, indicate that the optimal performance is achieved in broken-gap heterojunction devices. These results further demonstrate the efficacy of the heterojunction design in improving TFET drive current, but also suggest that novel device geometries [5] or material systems with direct band gaps (e.g. III-Vs [6], graphene nanoribbons [7]) may be needed to achieve the performance levels necessary for practical applications. References. [1] J. Appenzeller, et al., Phys. Rev. Lett., 2004, [2] O. Nayfeh, et al., IEEE Elect. Dev. Lett., 2008, [3] S. J. Koester, et al., unpublished, [4] S. Koswatta, et al., IEDM, 2009, [5] A. Bowander, et al., VLSI., 2008, [6] S. Mookerjea, et al., IEDM, 2009, [7] Q. Zhang, et al., IEEE Elect Dev. Lett., 2008. n+ poly

Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

This paper studies the leakage current components in embedded Si1-x,Gex, source/drain (S/D) p+-n junctions, with different Ge contents, varying between 20% and 35%. In addition, the impact of performing a highly doped drain (HDD) implantation before or after the selective epitaxial deposition of in situ highly B-doped S/D layers is investigated. It is shown that the lowest junction leakage is obtained for the post-epi HDD condition, and moreover, for the smallest active area size. As pointed out, this dependence is related with a window-size-dependent strain relaxation, induced by the ion-implantation-related defects.

Kinetics of Si incorporation into a Ge matrix for Si1−xGex layers grown by chemical vapor deposition

The growth rate and alloy composition of Si1−xGex layers grown in an industrial chemical vapor deposition (CVD) system have been analyzed as functions of the process parameters at a pressure enabling selective epitaxial growth. We systematically investigate the growth of Si1−xGex with 0.48<x<0.8, using GeH4∕SiCl2H2 partial pressure ratios up to 1.12, where the GeH4 flow was constant and the SiCl2H2 flow was varied. Epitaxial growth temperatures spanned from 350to600°C. The growth rate and alloy composition were limited by the surface reaction step with an activation energy of 1eV∕mol. A significant growth rate reduction is observed when increasing Si content. This feature is consistent with a passivation of the surface Si bonds with H and Cl atoms typical of chemical vapor deposition Si1−xGex layer growth. It is found empirically that x∕(1−x)∝pDCSΔn, Δn=0.32, where x is the Ge mole fraction and pDCS is the SiCl2H2 partial pressure. Then we tentatively develop a model to support the empirical laws found wi...

Selective Epitaxy of Si/SiGe to improve pMOS devices by recessed Source/Drain and/or Buried SiGe Channels

SiGe R. Loo, P. Verheyen, R. Rooyackers, C. Walczyk*, F.E. Leys, D. Shamiryan, P.P. Absil, T. Delande, A. Moussa, J.W. Weijtmans, R. Wise, V. Machkaoutsan, C. Arena, J. McCormack, S. Passefort, H. Sorada, A. Inoue, B.C. Lee, S. Hyun, S. Jakschik, and M. Caymax 1 IMEC, Kapeldreef 75, 3001 Leuven (Belgium), *also Universitat Siegen, Holderlinstrasse 35, 7068 Siegen (Germany), Texas Instruments Inc., 13560 North Central Expressway, Dallas (USA), ASM-Belgium, Kapeldreef 75, 3001 Leuven (Belgium), ASM-America, 3440 East University Drive, Phoenix, (USA), KLA-Tencor Corp. 160 Rio Robles, San Jose (USA), Matsushita assignee at IMEC, Samsung assignee at IMEC, Infineon assignee at IMEC

Influence of the Highly-Doped Drain Implantation and the Window Size on Defect Creation in p+/n Si1-XGex Source/Drain Junctions

This paper presents an investigation of the impact of a Highly Doped Drain (HDD) implantation after epitaxial deposition on Si1-xGex S/D junction characteristics. While the no HDD diodes exhibit the usual scaling of the leakage current density with Perimeter to Area (P/A) ratio, this is not the case for the HDD diodes, showing a smaller perimeter current density JP for smaller window size structures, corresponding with larger P/A. This points to a lower density of surface states at the Shallow Trench Isolation (STI)/silicon interface, which could result from a lower compressive stress. In order to examine the role of the HDD implantation damage, Transmission Electron Microscopy (TEM) inspections have been undertaken, which demonstrate the presence of stacking faults in small active SiGe regions. These defects give rise to local strain relaxation and, therefore, could be at the origin of the lower STI/Si interface state density. The window size effect then comes from the active area dependence of the implantation defect formation.