S.G. Thomas

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon

Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.

(\hbox{Si}_{1 - y}\hbox{C}_{y})

Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn-off mechanism in MOSFETs forces a fundamental trade-off between leakage power and performance when the voltage is reduced. Tunneling field effect transistors (TFETs) could overcome this limitation since these devices have been theoretically shown to be capable of subthreshold slopes < 60 mV/decade [1]. However, the band gap of silicon (1.12 eV) is too large to provide acceptable drive currents in Si-based TFETs. TFETs fabricated using Si/SiGe heterojunctions [2] have the potential for increased drive current since the type-II band alignment reduces the effective band gap for tunneling at the source electrode. In this talk, I will show experimental results on Si/SiGe heterojunction tunneling transistors (HETTs), along with quantum transport simulations on a variety of heterojunction TFET geometries, and then describe the implications of these results on the viability of the Si/SiGe material system for TFET fabrication. Si/SiGe HETTs. The devices were fabricated using a conventional CMOS process flow that was modified to allow the source and drain electrodes to be formed in separate processing steps. The devices utilized SOI starting substrates and a high-κ/poly gate stack. The n drain was formed by conventional As implantation and anneal, while the source electrode was formed by selective etching of Si underneath the gate electrode and regrowth of in-situ-doped p Si1-xGex. Typical Id vs. Vgs characteristics at room temperature for HETTs with source Ge concentrations of 7% and 25% are shown in Fig. 2 [3]. The improved performance for the devices with x = 25% over x = 7% provides a clear indication of the heterojunction benefit on TFET performance. However, the devices fall short of achieving sub-60 mV/dec subthreshold slopes or the necessary drive currents for practical applications. Broken-gap TFETs. In order to further explore the heterojunction band structure requirements for TFETs, quantum transport simulations are performance on a variety of HETTs with band alignment ranging from staggered to broken gap [4]. The results, shown in Fig.3, indicate that the optimal performance is achieved in broken-gap heterojunction devices. These results further demonstrate the efficacy of the heterojunction design in improving TFET drive current, but also suggest that novel device geometries [5] or material systems with direct band gaps (e.g. III-Vs [6], graphene nanoribbons [7]) may be needed to achieve the performance levels necessary for practical applications. References. [1] J. Appenzeller, et al., Phys. Rev. Lett., 2004, [2] O. Nayfeh, et al., IEEE Elect. Dev. Lett., 2008, [3] S. J. Koester, et al., unpublished, [4] S. Koswatta, et al., IEDM, 2009, [5] A. Bowander, et al., VLSI., 2008, [6] S. Mookerjea, et al., IEDM, 2009, [7] Q. Zhang, et al., IEEE Elect Dev. Lett., 2008. n+ poly

Source and Drain Stressors With High Carbon Content

This paper studies the leakage current components in embedded Si1-x,Gex, source/drain (S/D) p+-n junctions, with different Ge contents, varying between 20% and 35%. In addition, the impact of performing a highly doped drain (HDD) implantation before or after the selective epitaxial deposition of in situ highly B-doped S/D layers is investigated. It is shown that the lowest junction leakage is obtained for the post-epi HDD condition, and moreover, for the smallest active area size. As pointed out, this dependence is related with a window-size-dependent strain relaxation, induced by the ion-implantation-related defects.

Are Si/SiGe Tunneling Field-Effect Transistors a Good Idea?

We realized Impact Ionization Nanowire Multiple-gate Field- Effect Transistors (I-MuGFETs or I-FinFETs) having a multiple- gate/nanowire-channel architecture to exploit the superior gate-to- channel coupling for reduced breakdown voltage VBD and enhanced device performance. The first p-channel Impact Ionization MOS transistor (I-MOS) having in situ doped source was also demonstrated. An in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces VBD and enhances the on-state current Ion. A further improvement was also made by incorporating strained Si1-yCy impact-ionization region (I-region) and in situ doped Si1-yCy source, leading to further reduction in VBD and enhancement in Ion. This is due to strain- induced reduction of the impact-ionization threshold energy Eth. In addition, excellent subthreshold swing of below 5 mV/decade at room temperature was achieved for all devices.

Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

Strain is introduced in the fabrication of complementary metal-oxide-semiconductor devices to enhance their channel region carrier mobility [1]. Epitaxial Si1−xGex (15–30at% Ge) or Si1−xCx (1–2at% C) are typical stressor materials. As Ge has a 4% larger lattice constant (0.566 nm) than Si (0.543 nm), Si1−xGex deposited in the source/drain (S/D) regions will induce compressive strain in the Si channel, while Si1−xCx in the S/D will induce tensile strain in the channel [2].

P-Channel I-MOS Transistor featuring Silicon Nano-Wire with Multiple-Gates, Strained Si 1-y C y I-region, in situ doped Si 1-y C y Source, and Sub-5 mV/decade Subthreshold Swing

The semiconductor industry is being pushed to develop smaller and faster devices as well as increase functionality. As such, a key part of the long-term technology roadmap will include integrating disparate semiconductor materials to provide superior performance and functionality. However, any viable technology solution must not only provide performance, but also cost-effectiveness and scalability.

Strain study in transistors with SiC and SiGe source and drain by STEM nano beam diffraction

In this paper, we report the first demonstration of n-channel FinFETs with in-situ doped silicon-carbon (Si1-yCy or SiC:P) source and drain (S/D) stressors. New key features incorporated in this work for performance enhancement includes record-high substitutional carbon concentration Csub of 2.1%, high in-situ phosphorus doping concentration in S/D, extended Pi -shaped S/D stressors that wrap around the Si fin for maximum lattice interaction, lateral stressor encroachment under the spacer for closer promixity to channel region for maximum channel stress as well as reduced S/D extension resistances.

Direct Heterointegration of III-V Materials on Group IV Substrates

We report the first demonstration of an n-channel transistor (n-FET) featuring a compliant Si_0.75Ge_0.25 stress transfer layer (STL) and in situ doped Si_0.98C_0.02 source/drain (S/D) stressors for performance enhancement. Due to the stress coupling between Si_0.98C_0.02 and the compliant SiGe STL, additional strain is imparted to the Si channel. Devices with gate length LG down to 30 nm were fabricated. The enhanced strain effects resulted in 65% drive current improvement in strained n-FETs over control n-FETs for a given DIBL of 0.20 V/V.

Strained FinFETs with In-situ Doped Si 1-y C y Source and Drain Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content

We report a new source/drain-extension-last (SDE-last) process flow to incorporate in situ doped and lattice-mismatched source/drain (S/D) stressors extremely close to the channel edge for increased strain and reduced series resistance. This process enables the introduction of S/D stressors with much larger than reported lattice-mismatch at the end of the front-end process, thereby minimizing the thermal budget experienced by highly strained heterostructures which could possibly relax strain. For the first demonstration of this concept, an in situ phosphorus- doped silicon-carbon (SiCP) SDE was employed and integrated in a SOI N-FET. A record-high substitutional carbon concentration of 2.1% was used to realize very significant strain effects.

Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si 0.98 C 0.02 source/drain stressors for performance enhancement

This paper presents an investigation of the impact of a Highly Doped Drain (HDD) implantation after epitaxial deposition on Si1-xGex S/D junction characteristics. While the no HDD diodes exhibit the usual scaling of the leakage current density with Perimeter to Area (P/A) ratio, this is not the case for the HDD diodes, showing a smaller perimeter current density JP for smaller window size structures, corresponding with larger P/A. This points to a lower density of surface states at the Shallow Trench Isolation (STI)/silicon interface, which could result from a lower compressive stress. In order to examine the role of the HDD implantation damage, Transmission Electron Microscopy (TEM) inspections have been undertaken, which demonstrate the presence of stacking faults in small active SiGe regions. These defects give rise to local strain relaxation and, therefore, could be at the origin of the lower STI/Si interface state density. The window size effect then comes from the active area dependence of the implantation defect formation.