Pieter Palmers

A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS

This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The analysis of the major distortion mechanisms in the switched current cell allows the derivation of a design strategy for maximum linearity. This strategy is extended to include the power consumption of the switch drivers in function of the switched current cell design. To minimize the digital power consumption, low-power implementations of the thermometer decoder and switch driver circuits are introduced.

Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies

This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide a performance tradeoff. MOJITO defines a space of possible topologies as a hierarchically organized combination of trusted analog building blocks. To minimize the setup burden: no topology selection rules or abstract behaviors need to be specified, and performance calculations are SPICE-based. The search algorithm is a novel multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation. Results are shown for a space having 3528 one- and two-stage operational amplifier topologies.

Parallel-path digital-to-analog converters for Nyquist signal generation

Nyquist-rate digital-to-analog converters (DACs) can generate frequencies up to half the sampling frequency. It is, however, impractical to generate such high frequencies. Due to its nature, the converter will not only generate the desired signal itself but also, often undesired, image frequencies. For frequencies near the Nyquist frequency, an image with almost exactly the same amplitude appears very close to the signal. An extremely steep filter is required. Therefore, real-life systems do provide oversampling to locate the Nyquist image further away from the wanted signal. In practice, the signal frequency has to be reduced if the maximum sampling rate is reached. We propose a technique that conversely removes this Nyquist image so that only further away Nyquist images with lower amplitudes have to be filtered off. The proposed technique is applied to the design of a dual 6-bit binary current-steering DAC running at 250 MS/s.

Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks

This paper presents MOJITO, a system that performs structural synthesis of analog circuits, returning designs that are trustworthy by construction. The search space is defined by a set of expert-specified, trusted, hierarchically-organized analog building blocks, which are organized as a parameterized context-free grammar. The search algorithm is a multiobjective evolutionary algorithm that uses an age-layered population structure to balance exploration versus exploitation. It is validated with experiments to search across >;100 000 different one-stage and two-stage opamp topologies, returning human-competitive results. The runtime is orders of magnitude faster than open-ended systems, and unlike the other evolutionary algorithm approaches, the resulting circuits are trustworthy by construction. The approach generalizes to other problem domains which have accumulated structural domain knowledge, such as robotic structures, car assemblies, and modeling biological systems.

Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy

This paper presents MOJITO-R, a tool that performs variation-aware structural synthesis of analog circuits. It returns trustworthy topologies by searching across a space of thousands of possible topologies defined by hierarchically organized analog structural building blocks. ldquoStructural homotopyrdquo conducts search at several objective-function tightening levels (numbers of process corners) simultaneously. Multiobjective evolutionary search returns sized topologies which trade off power, area, performances, and yield. An experimental validation run returned 78 643 Pareto-optimal designs, having 982 sized topologies with various specification/yield combinations. A decision tree is extracted to visualize the performance-topology relationship.

Massively multi-topology sizing of analog integrated circuits

This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, MOJITO, which searches through 3500 topologies defined by a hierarchically-organized set of 30 analog blocks. This paper improves MOJITOs results quality via three key extensions. First, it enlarges the block library to enable symmetrical transconductance amplifiers and more. Second, it improves initial topology diversity via optimization-based constraint satisfaction. Third, it maintains topology diversity during search via a novel multi-objective selection mechanism, dubbed TAPAS. MO-JITO+TAPAS is demonstrated on a problem with 6 objectives, returning a tradeoff holding 17438 nondominated designs. The tradeoff is comprised of 152 unique topologies that include the newly-introduced topologies. 59 designs across 12 topologies designs outperform an expert-designed reference circuit.

Automated extraction of expert knowledge in analog topology selection and sizing

This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. The methodology is to take a data-mining perspective on a Pareto Optimal Set of sized analog circuit topologies, then doing: extraction of a specs-to-topology decision tree; global nonlinear sensitivity analysis on topology and sizing variables; and determining analytical expressions of performance tradeoffs. These approaches are all complementary as they answer different designer questions. Once the knowledge is extracted, it can be readily distributed to help other designers, without needing further synthesis. Results are shown for operational amplifier design on a database containing thousands of Pareto Optimal designs across five objectives.

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3

This paper presents a 1.2-2.6GHz 2×12 bit Direct Digital RF Modulator (DDRM) realized in 28nm CMOS. The digital cartesian transmitter features baseband sampling speeds up to LO. The intrinsically linear architecture features current-mode operation at 25% duty cycle, which requires less predistortion than existing digital transmitters. The applied digital intensive LO modulation reduces the power consumption of the LO distribution. Except for the output stage at 1.8V, the modulator is powered from 0.9V supply. The DDRM features an OP1dB of 15.5dBm. At 3.9dBm output power, the un-calibrated C-IM3 is better than -42dBc, while the image is below -49dBc. With a simple 1D calibration the C-IM3 can easily be improved to below -58dBc. The modulators peak drain efficiency at 17.5dBm is 34%.

A low-power mixing DAC IR-UWB-receiver

This paper introduces a novel receiver architecture for low-power IR-UWB receivers in the 3.75-4.25 GHz band. The receiver correlates the incoming pulse with an approximated pulse template in the analog domain. The template is learnt digitally and transferred to the analog domain via a low resolution DAC. The paper presents the design of the mixing DAC that implements the downconverter, DAC and correlator which consumes only 875 uW in 90 nm CMOS technology. The DAC receiver topology requires 4 dB less energy per incoming bit in comparison with current state-of-the-art IR-UWB receivers.

A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

This paper presents a delta-sigma current-steering digital-to-analog converter implemented in a standard 130 nm CMOS technology. The 5-bit core DAC provides 13-bit static linearity without calibration, using only 0:44 mm2. The delta-sigma converter achieves 68 dB SFDR over a 100 MHz signal bandwidth at 1 GHz sampling frequency. A novel very low power thermometer decoder was used, resulting in a power consumption of 11 mW. In terms of power efficiency this converter outperforms all comparable D/A converters published in open literature. The design demonstrates the viability of multi-bit delta-sigma D/A converters as an alternative for Nyquist-rate DACs in highly integrated broadband applications. It also shows that in deep sub-micron processes the use of a delta-sigma converter extends the usable bandwidth for D/A converters.