Koen Cornelissens

Design Considerations for Cascade

This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter.

\Delta \Sigma

In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1-2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8-14 dBm, while drawing only 22-40 mW in various operating modes.

ADC's

This paper presents a switched-capacitor ΔΣ analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3–1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped switch solves the non-linearity issues of low-voltage transmission gates. The higher flicker noise of nanoscale CMOS technologies is reduced by applying chopping to the first amplifier input pair.

A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection

A SAW-less discrete-time superheterodyne receiver (RX) with multi-stage harmonic rejection in 28nm CMOS, featuring highly linear LNTA, employs a novel blocker-resilient octal charge-sharing band-pass filter to achieve low power consumption. The RX features NF of 2.1 to 2.6 dB, and IIP3 of 8 to 14 dBm, while drawing only 24 to 37 mW in different operating modes.

A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS

This paper presents a switch bootstrapping technique for very high sampling frequencies. The circuit has been implemented in a switched capacitor delta sigma A/D converter operating at 400 MHz in a 0.18 μm CMOS technology. The high sampling frequency allows to use a high oversampling ratio, resulting in a SNR of 53 dB and signal bandwidth of 3.125 MHz with a simple singleloop second order topology. Measured SNDR is 47.5 dB, while the core power consumption is 12 mW.

A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS

In comparator-based switched-capacitor circuits, OTAs are replaced by comparators and current sources. Instead of an OTA forcing a virtual ground condition, a comparator steers current sources until it detects a virtual ground. Different possibilities to use this principle in a ΔΣ A/D converter are evaluated. A pseudo-differential implementation with preset minimizes the requirements for the comparator and the current source. Due to the operation of the circuit, feed-back noise-shaping filters with half delay integrators are preferable. An implementation of a comparator-based switched-capacitor ΔΣ A/D converter in a 1 V, 90 nm CMOS technology demonstrates the feasibility.

A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC

In this paper a cascade 3-1 feedforward DeltaSigma topology is introduced and compared with other fourth order DeltaSigma ADCs. The third order first loop reduces problems with quantization noise leakage from classical 2-1-1 or 2-2 cascade topologies, leading to lower OTA specifications. Compared to a fourth order single loop converter, more aggressive noise shaping is possible, leading to a lower OSR for the same SNR. By comparing the required OSR and OTA specifications for different fourth order structures, the optimal topology can be chosen depending on the ratio Pdig/Pan. The cascade 3-1 topology is the most favorable choice when this ratio lies between 0.37 and 1.06.

Comparator-Based Switched-Capacitor Delta-Sigma A/D Converters

A voltage modulator using only switched capacitors is presented. Depending on the desired output voltage a combination of capacitances is connected to the output capacitance, to increase or decrease the output voltage. The circuit is capable of delivering output signals within a frequency range from DC up to 100 kHz, with all harmonic distortion components below 30 dB. Operating at a supply voltage of 1.8 V, it delivers a maximum output power of 32mW with an efficiency of 72%.