Maarten De Bock

Calibration of DAC Mismatch Errors in

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit ΣΔ-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration.

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A 4th-order 40MHz Bandwidth 12bit continuous-time delta-sigma modulator is presented in this paper. A shaped SC DAC with reduced peak current is proposed to relax the OTA slewing requirement, consuming no extra hardware or power. The DAC static and dynamic mismatches are eliminated by lookup table based digital calibration. With 1.2V supply and 69.6mW power in 90nm CMOS, the modulator achieves excellent SFDR of 84.2dB and 72.9dB peak SNDR at 960MHz clock frequency, corresponding to a FoM of 0.24pJ/Step. The core circuit area is about 0.28mm2.

ADCs Based on a Sine-Wave Measurement

We present a very compact analog-to-digital convertor (ADC) for use as a standard cell. To achieve an inherent accuracy of at least 12-bits without trimming or calibration, extended counting A/D-conversion is used. Here, the circuit performs a conversion by passing through two modes of operation: first it works as a 1st-order incremental convertor and then it is reconfigured to operate as a conventional algorithmic converter. This way, we obtain a Nyquist-rate converter that requires only 1 operational amplifier and achieves 12-bit accuracy performance in 13 clock cycles with 9 bit capacitor matching. The circuit is designed in 0.18 μm CMOS with a thick oxide option. The resulting analog core occupies a chip area of only 0.011 mm2 and the complete digital control and reconstruction logic (including additional test features and storage registers) is 0.02 mm2. The analog blocks of the circuit consume 1.2mW and the digital 0.4mW. At a sample rate of 1 MS/s, the peak SNDR is 74.5dB and the dynamic range is 78dB, constant over the Nyquist band. The worst-case integral non-lineairity (INL) is within ±0.55 LSB.

A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS

Recently nearly exact expressions for the distortion in a commonly used family of Pulse Width Modulators (PWMs) known as Asynchronous Sigma Delta Modulators (ASDMs) were presented. Such an ASDM consists of a feedback loop with a schmitt-trigger (or a comparator), and a continuous time loop filter. However these previous results are not yet practically applicable because the effect of unavoidable loop delay (e.g. in the schmitt trigger) was not taken into account. Therefore we now present a more general theory that is also valid when there is a nonzero loop delay. A comparison of the resulting equations with computer simulations demonstrated a very good matching, confirming the validness of the theory. This way, a designer can now easily understand the relationship between the loop filter dynamics and the linearity of an ASDM.

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

We present an offline calibration method to correct the non-linearity due to DAC element mismatch in distributed feedback SigmaDelta-modulation A/D-converters. The improvement over previous methods is that not only the first feedback DAC is calibrated, but also the DACs that are coupled to later stages can be calibrated as well. This is needed in the case of Sigma Delta modulators with a low OSR, where the contribution of the second feedback DAC should not be neglected. The technique is based on a calibration measurement with a two-tone input signal.

Analyzing distortion in ASDMs with loop delay

This paper presents the design of a second order double-sampling split path Sigma Delta modulator with cross noise-coupling. The power budget for the double-sampling is reduced by using bilinear integrators, while cross noise-coupling between the two modulator loops increases the noise shaping to third order. The implementation of the noise-coupling is incorporated into the second integrator using a novel delaying feed-forward circuit. The complete modulator is integrated in a 130nm CMOS technology and operates at a 120 MHz clock frequency. It achieves 77.8dB dynamic range and 71.4dB SNDR over a 5MHz bandwidth.