Pietro Buccella

Impact of enhanced contact doping on minority carriers diffusion currents

Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentration discontinuity of these contact regions can have a big impact on parasitic diffusion currents of minority carriers. This work gives a description of these effects by device physical simulations of PN junctions under different injection levels of minority carriers. The perturbation of boundary conditions for electrons diffusion is also studied inside the substrate bulk in case a highly-doped substrate is used for high-voltage technologies.

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

Substrate noise modeling with dedicated CAD framework for smart power ICs

In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation into the substrate is not considered in most of existing circuit simulators. In this paper, a novel computer-aided design tool for substrate parasitic extraction is proposed. A simple circuit with an injecting and a collecting N-wells over a P-substrate is studied. With the distance between the wells varying, the lateral bipolar effect is illustrated. The spectre simulation results of extracted substrate equivalent circuit are compared to a TCAD simulation results. The comparison shows an acceptable relevant error. However, the simulation time was reduced by approximately 1400 times with respect to the TCAD.

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow.

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult to implement and to verify during the design of a complex Smart Power circuit. These rules are often based on the physical device simulations or on the empirical results extracted from predefined benchmark structures. In this paper, a novel approach is proposed for designing robust circuits integrating accurate and specific analysis of substrate couplings already into the design flow. First, substrate currents injected by power transistors are discussed to show the spatial distribution of voltage and currents into the substrate. A set of guidelines to optimize substrate currents is presented as a summary of the studied test cases. Then, an H-Bridge output driver was implemented in a 0.35- μm HVCMOS technology to investigate substrate currents by both measurements and simulations. Reverse currents were deliberately injected into the chip to activate substrate lateral and vertical parasitic bipolar junction transistors and measured data closely match circuit simulation results in both cases.

Spice simulation of substrate minority carriers propagation with equivalent electrical circuit

This paper presents an equivalent electrical circuit for one dimensional substrate minority carriers spice simulation. The electrical circuit parameters are extracted from substrate meshing applying the finite difference method. This model is derived from a linearization of drift-diffusion equations and not from the closed form solution. Further, the proposed circuit is solved with available SPICE simulators because of electrical analogies with physical quantities. Spice simulation results are compared with device simulator results. The accuracy of the model is dependent on the number of the discretization elements used. The minority carrier diffusion current is included automatically in the total substrate current computation.

Substrate modeling to improve reliability of high voltage technologies

In Smart Power ICs there is the need of new substrate models to be integrated in the design flow of power circuits. This work reports the latest results regarding the substrate modeling methodology based on three-dimensional lumped components extraction of diodes, resistors and contacts. The substrate network including lateral and vertical parasitic bipolar transistor can be automatically created from any chip layout including temperature and geometry variations. In such a way fast dc and transient analysis can be carried out in early design stages to improve reliability of high voltage ICs. Since the high variability and complexity on modern Smart Power technologies, a flexible model is required. This work discusses all the features related to technology variations. Circuit simulator results are then compared with TCAD simulations.

Spice simulation of passive protection in smart power ICs

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists in integrating a new substrate model in spice to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.

Optimization strategy of numerical simulations applied to EPFL substrate model

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

Modeling avalanche breakdown for ESD diodes in integrated circuits

Usually device compact models do not include breakdown mechanisms which are fundamental for ESD protection devices. This work proposes a novel spice-compatible modeling of breakdown phenomena for ESD diodes. The developed physics based approach includes minority carriers propagation and can be embedded in the simulation of parasitic substrate noise of power devices. The model implemented in VerilogA has been validated with device simulations for a simple structure at different temperatures showing good agreement and robust convergence.