Adil Koukab

Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs

The substrate noise coupling problems in todays complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

LC-VCO Design With Dual-

A VCO topology with a high at RF and low gm at low frequencies (LF) is presented. A high gm(RF) improves start-up conditions, and a low gm(LF) enables a significant improvement of the phase noise and the power supply rejection. The VCO with a modified prescaler was implemented in 0.25 μm CMOS technology. The measured phase is at 1 MH offset, when the VCO works at 3 GHz and consumes 7.5 mW. The corresponding figure of merit is 189.2 dBc/Hz/mW.

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The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a suite of commercial tools in combination with a high-speed extractor based on an innovative semi-analytical method to deal with noise coupling problems, and enable RF designers to achieve a first silicon-success of their chips. The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver demonstrated.

, Boosted for RF Oscillation and Attenuated for LF Noise

A new type of CMOS compatible photodetector, exhibiting intrinsic light-to-time conversion, is proposed. Its main objective is to start the time-to-digital conversion directly at its output, thereby avoiding the cumbersome analog processing. The operation starts with an internal charge integration, followed by a positive feedback, and a sharp switching-current. The device, consisting of a deeply depleted MOS structure controlling the conduction of a forward-based PN diode, is presented and its operation explained. TCAD simulations are used to show the effects of semiconductor parameters and bias conditions. The photodetector and its detection circuit are designed and fabricated in a 0.18µm CMOS process. Measurements of this new device under different biasing and illumination conditions show highly promising properties in terms of linearity, internal gain, and noise performances.

Analysis and optimization of substrate noise coupling in single-chip RF transceiver design

This paper presents a compact model for LINC (linear amplification with non linear components) transmitters an their power combiners. The study focuses on the detrimental effect of the transmission line nonidealities. A mathematical description of the system that considers these nonidealities is proposed. The developed analytical expressions can be used to optimize, analyze and build pre-distortion algorithms for this family of transmitters. The efficiency and linearity are reexamined in light of the new analytical expressions of the model.

Hybrid MOS-PN photodiode with positive feedback for pulse-modulation imaging

A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD) and WLAN (802.11a/b/g) standard is developed. The implementation is achieved in 0.25/spl mu/m BiCMOS-SiGe process. The measured tuning range is higher than 1GHz (3.05GHz to 4.1 GHz) exceeding by 25% the specifications. The VCO exhibits a phase noise of -118 and -125 dBc/Hz measured respectively at 400KHz and 1MHz offsets while drawing only 2.5 mA from 2.5 V supply. The measured phase noise at 400 KHz offset from the PCS 1900/DCS1800 and the GSM850/900 carriers are respectively -124 dBc/Hz and -130dBc/Hz.

Analysis and modeling of on-chip power combiners and their losses in LINC transmitters

This paper presents a fully Digital Pixel Sensor (DPS) front-end with a focus on its noise modelling and analysis. The design relies on a new type of photodetector displaying an intrinsic light-to-time conversion. Avoiding the pixel level analog processing improves significantly the overall performances of the image sensor. The photodetector as well as its front-end circuit are described. The noise performances and their variations with the physical and bias conditions are theoretically and experimentally studied.

Multistandard carrier generation system for quad-band GSM/WCDMA (FDD-TDD)/WLAN (802.11 a-b-g) radio

Phase-noise mechanisms in cross-coupled LC voltage-controlled oscillators (VCOs) are reviewed based on a physical understanding of reactive power imbalances in the tank and in the active part. These phenomena are proven to be the predominant phase-noise degradation mechanism in relatively low- and high-current operations. Based on this analysis, a technique to suppress these detrimental effects is developed and implemented in an LC VCO design. The measured results confirm the dependencies predicted by the analysis, and the usefulness of the proposed technique to simultaneously optimize the phase noise at high and low offset frequencies. The measured VCO tuning range is 600 MHz, ranging from 2.4 to 3 GHz. The VCO-prescaler circuit exhibits a phase noise from - 88 to -92 dBc/Hz at 15 kHz and from -155 to -160 dBc/Hz at 10 MHz, when the power consumption is 6 and 10 mA for the VCO and 2 mA for the prescaler, and the power supply is 2 V.

Design of a direct light to time converter and its noise analysis

The unprecedented impact of noise coupling on Mixed-Signal Systems-On-a-Chip (MS-SOC) functionality, brings a new set of challenges for Electronics Design Automation (EDA) tool developers. In this paper, we propose a new approach which combines a thorough physical comprehension of the noise coupling effects with an improved Boundary-Element-Method (BEM) to accelerate the substrate model extraction and to avoid the dense matrix storage. The low computational efforts required, as well as speed and accuracy reached, makes this method a highly promising alternative to verify complex MS-SOCs.

Reactive Power Imbalances in LC VCOs and Their Influence on Phase-Noise Mechanisms

A novel power amplifier (PA) supply technique that clearly reduces the noise at the bond-wires is presented. The method takes advantage of the filtering/matching network at PA output to suppress the HF supply noise. This approach is particularly suitable to help a single-chip integration of some applications such as RF identification or wireless local-area networks.