Pietro Cantu

Sub-k1 = 0.25 lithography with double patterning technique for 45-nm technology node flash memory devices at λ = 193nm

An enormous pressure is currently put on Resolution Enhancement Techniques to meet the deadline for the development of high density memory devices. The prevailing conviction is to consider water immersion lithography as the choice for manufacturing 45nm technology node devices. Even if a huge effort to face immersion specific issues has been done (on defectivity, micro-bubbles, contamination, overlay control, hyper NA imaging, birefringence), a technology solution to image the desired features and densities must be available till now in order to anticipate all the steps involved in the process integration before the complete assessment of the immersion infrastructure. Moreover, the forecasted solutions for 32nm and 22nm technology nodes remain uncertain, strongly depending on current and near future development of high index fluids for immersion lithography and EUV availability. These temporal lacks of technology options are forcing scanner suppliers and IC manufacturers to include also double exposure in the group of viable choices for future development. Double patterning (double exposure and double etch) is surely a fascinating solution for overcoming the physical resolution limit of k1 = 0.25 of imaging systems. Various papers in these last two years demonstrated an increasing interest in the exploration of such kind of technique to extend as much as possible ArF dry exposure tools. Though the concept of this technique is simple and well known, there are various technical issues which must be solved before moving to a real implementation in the manufacturing phase. In this paper we want to present the experimental results of the application of double patterning to the definition of a 45nm technology node Flash memory device, reaching a k1 ~ 0.20 using 193nm dry lithography. Flash memory design introduces imaging critical points in several levels: active, contacts, and first metallization. For each of these layers, a dedicated study of double exposure has been performed in order to develop a combined litho-etch process to pattern the requested features density. Different issues will be reported, related to process choices (hard mask, resist compatibility), overlay performances, OPC and layout decomposition. Experimental process windows of dedicated test masks with lines and spaces and contact holes are shown. A deep study on overlay performance and possible optimizations has been performed and will be reported. Finally, we will demonstrate that double exposure technique can be used to anticipate process integration of critical lithography steps for high density memory devices at 45nm technology node.

Full-chip implementation of IDEALsmile on 90nm node devices with ArF lithography

Summary form only given. According to sizes dictated by ITRS roadmap, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. To overcome this issue Canon, in 2002, introduced a new technology, entitled lDEALSmile1i2 (Innovative Double Effective source Aided Lithography with Single Mask Implemented Lithographic Enhancement), that was proven to be able to define contacts with high resolution and sufficiently large through pitch? process window using a binary mask, cheap and simple to be manufactured, modified illumination and single exposure, without any negative impact on throughput and no increase of cost of ownership, The technology was further improved in 2003 with the introduction of Enhanced-IDEALSmile4 that, in certain conditions, allows achieving even higher contrast, and increased DOF thanks to three beam interference obtained with special shifted arrangement of dummy patterns without modifying optimized illumination shape.

Evaluation of Hitachi CAD to CD-SEM metrology package for OPC model tuning and product devices OPC verification

Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193nm resists, much more sensitive to SEM e-beam exposure if compared to 248nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues. In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy. The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

Impact of medium and long range effects on poly gate patterning

CD control specifications for poly gate patterning are becoming tighter and tighter: latest revisions of International Technology Roadmap for Semiconductors require a CD control in the range of 2.2nm (3σ) for the 65nm technology node. In this scenario model-based Optical Proximity Correction methodologies, traditionally developed to address optical and resist development effects, had to face the challenge to correct post-resist processing steps with the aim to guarantee a final effective CD control within expected specifications. Complex 1D rule-based corrections, applied in the past, are no more adequate to capture complex 2D effects becoming relevant starting from 90nm node; only a more comprehensive 2D model-based approach can correctly predict, and so compensate, complex physical and chemical etch phenomena inducing CD variations. In this paper we experimentally study the impact of medium and long range etch effects on poly gate patterning, trying to identify their nature and impact on intra-die CD variations. Different innovative model-based approaches for lithography and etch effects compensation are evaluated and compared on Flash memory circuitry (90, 65 and 45 nm node) with the aim to reduce intra-die CD dispersion component. Finally the impact of local and global pattern density on etch behavior is studied in relation to different dummy placement strategies.

Characterization of metal line-width variation in via first dual-damascene approach and its modeling using machine learning artificial neural network algorithms

Line patterning, in via first dual damascene approach, is conditioned by vias density: bottom anti–reflective coating (BARC), used to minimize thin film interference effects by reducing reflected light, and photoresist reflow into vias, leading to materials thickness variation, and so to unwanted modification of metal lines critical dimension (CD), due to local reflectivity change and to swing effect. Aim of the work is to assess CD variations to be expected at device level when applying via first integration scheme, in order to compensate them, where and when feasible, or to setup restrictions to vias density at design level, forbidding critical configurations that might lead to patterning failures. The paper presents an experimental characterization of metal line CD variation as a function of vias density based on the study of a test pattern, designed to explore a wide variety of vias and metals respective configurations, and investigates different approaches to model and predict CD deviations from expected targets. Vias densities, or their convolution with specific kernels, are extracted using conventional design rule check (DRC) tools, and are used as predictors to model metal lines CD variation behavior. Simple via density computation is not able to capture the effect, so we propose a flow, based on machine learning artificial neural network algorithms, able to predict metal line width variations to be expected on product devices as a function of the vias pattern underneath.

Combined Mask and Illumination Scheme Optimization for Robust Contact Patterning on 45nm Technology Node Flash Memory Devices

Immersion Lithography is the most important technique for extending optical lithographys capabilities and meeting the requirements of Semiconductor Roadmap. The introduction of immersion tools has recently allowed the development of 45nm technology node in single exposure. Nevertheless the usage of hyper-high NA scanners (NA > 1), some levels still remain very critical to be imaged with sufficient process performances. For memory devices, contact mask is for sure the most challenging layer. Aim of this paper is to present the lithographic assessment of 193nm contact holes process, with k1 value of ~0.30 using NA 1.20 immersion lithography (minimum pitch is 100nm). Different issues will be reported, related to mask choices (Binary or Attenuated Phase Shift) and illuminator configurations. First phase of the work will be dedicated to a preliminary experimental screening on a simple test case in order to reduce the variables in the following optimization sections. Based on this analysis we will discard X-Y symmetrical illuminators (Annular, C-Quad) due to poor contrast. Second phase will be dedicated to a full simulation assessment. Different illuminators will be compared, with both mask type and several mask biases. From this study, we will identify some general trends of lithography performances that can be used for the fine tuning of the RET settings. The last phase of the work will be dedicated to find the sensitivity trends for one of the analyzed illuminators. In particular we study the effect of Numerical Aperture, mask bias in both X and Y direction and poles sigma ring-width and centre.

Alternated phase shift mask for 45nm node contact holes patterning

Among other memory products FLASHes are becoming a technology driver in term of design rules aggressiveness for dense structures. Upcoming revisions of ITRS roadmap forecast 45nm technology node introduction for FLASHes one year ahead (2006) compared to DRAMs (2007). In this scenario the basic development of 45nm process requires patterned samples starting from the end of 2005. Waiting for hyper high NA ArF immersion tools availability, different RET solutions based on the existing lithography platforms have been evaluated with the aim to provide patterned samples for process modules development. Our paper is focused on 45nm node contact holes, certainly considered one of the most challenging layers in the technology assessment: various RET strategies will be briefly discussed and particular attention will be dedicated to alternating phase shift mask option. Strong PSM approach has been already proposed in the past as viable solution for 65nm node contact holes patterning using ArF tools; here we discuss problems related to its extension down to 45nm node (with dry equipments), in ultra low k1 regime and close to the physical limit of 0.25 k1. The paper addresses main challenges related to the application of an alt PSM approach to a full chip FLASH design, suggesting possible solutions for assist features generation and phase assignment. Different strategies to compensate for the well known phase imbalance phenomena have been selected by using fully rigorous 3D optical simulations. Finally preliminary printing test will be shown. Lithography performances (Minimum resolution, Process window, contact profile) will be compared with conventional RET techniques.

Demonstration of a new mask structure using a bonded hard pellicle

As 193 nm lithography appears to be a long term solution for wafer patterning, we expect new resolution enhancement coming from advanced mask technologies. We have studied an assembly technique that could increase mask capability towards advanced wafer patterning. This paper presents a proof of concept for the use of bonded mask, obtained with two plates assembled together. The initial application targeted here is an alternative solution to pellicle. A special process has been worked out to obtain bonded test samples. Based on the knowledge of silicon wafer bonding techniques, we have developed a process that allows bonding of fused silica square plates. Constant progress allowed us to use specific materials used in mask manufacturing, such as chromium and fused silica, and also specific square shapes and rather large thickness. The final demonstrator is a Chromium on Glass mask (COG), on which a hard pellicle has been bonded without any additional material. The pellicle was 0.5 mm thick and 100 mm in diameter. This test sample has been qualified in a 248 nm AIMS tool. We made comparative measurements on different occurrence of the same chip, covered or not covered by the pellicle. We have shown evidence of induced spherical aberration for conventional illumination and this has been confirmed by simulation. Image fidelity was proven for positive and negative features. Through focus image capture showed that process windows were not impacted by the hard pellicle.

Device based evaluation of electron projection lithography

As we move technology further and further down the geometry scale we are coming upon imaging situations where our use of existing optical lithography is being questioned due to the lack of process margin in manufacturing lines. This is especially apparent in the imaging of contacts where memory devices, that generally have the densest arrays of these features, may no longer be able to print the desired features. To overcome this it is necessary to either modify the design, a very expensive and time consuming process, or find an imaging process capable of printing the desired features. Electron Projection Lithography (EPL) provides an option to print very small features with a large process margin. In this paper we detail the performance of both memory and logic based designs in an EPL process. We detail the manufacture and results of stencil mask manufacture. Data is also presented showing the imaging results (DOF, exposure latitude, pattern transfer) of features down to 50nm imaged on Nikon’s EB1A tool.

Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.