Pietro Monsurrò

Linearization Technique for Source-Degenerated CMOS Differential Transconductors

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption.

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band.

Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches.

Exploiting the Body of MOS Devices for High Performance Analog Design

With the progressive reduction of MOS transistors minimum dimension and their associated supply voltages, the body terminal-considered in the past as an exclusive source of unwanted second order effects-has been advantageously exploited by digital designers and is also becoming an attractive opportunity for the implementation of high-performance analog integrated circuits. In this paper, we will discuss some techniques that can be applied to many conventional analog building blocks in order to improve their performance (such as gain and linearity) and/or decreasing their supply demand. Experimental prototypes have been implemented and tested, showing that the proposed techniques are promising candidates for enhanced analog IC design in nanoscale technologies.

Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters

We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conversion, even in the presence of wideband input signals and signals beyond the first Nyquist band. The proposed algorithm improves a previous work by the authors by allowing higher precision, particularly in the case of many interleaved channels and large mismatches. Accuracy improves by 3–8 bits with respect to the previous algorithm and up to 10 bits with respect to the uncalibrated case.

A class-AB flipped voltage follower output stage

In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10µA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has −50dB HD2 and −60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns.

A model for the distortion due to switch on-resistance in sample-and-hold circuits

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration

Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two previously published calibration algorithms for the correction of bandwidth mismatch is shown. The proposed models can thus be used to simulate subsampling TI-ADCs and their calibration algorithms.

88- A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration.