Pil-Ho Lee

A 10-bit 20-MS/s asynchronous SAR ADC with controllable analog input voltage range and meta-stability detection circuit

A 10-bit 20-MS/s asynchronous SAR ADC, which has a controllable analog input voltage range and a meta-stability detection circuit, is proposed. The proposed SAR ADC with the area of 0.095 mm2 is implemented using a 130-nm CMOS process with 1.2-V supply. The measured peak ENOBs for the full rail-to-rail ±1.2V (peak-to-peak) differential sinusoidal input signal is 9.56 bits. The FoM achieves 41 fJ/conversion-step.

0.5 kHz–32 MHz digital fractional-N frequency synthesizer with burst-frequency switch

A digital frequency synthesizer is proposed to support the burst-frequency switch for a motion controller. The proposed digital frequency synthesizer consists of a phase-locked loop (PLL) generating a 63-phase clock with a frequency of 128 MHz and a programmable open-loop fractional divider. It generates an output clock with a frequency resolution of 0.1% over a frequency range from 0.5 kHz to 32 MHz. The programmable open loop fractional divider generates an output clock such that its frequency is synthesized by periodically selecting the phase interpolated clock from the 63-phase clock of the PLL according to a digital control code. The frequency switching operation is performed within one cycle of the output clock owing to the operation of the phase selection of the open-loop fractional divider. The proposed digital frequency synthesizer is implemented using a 0.25 μm CMOS process with a 2.5 V supply. The measured rms time jitter of the output clock with 16 MHz frequency is approximately 8.06 ps.

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal integrity of high-speed signals for a chip-to-chip interface with a source-synchronous clocking scheme. The proposed OCMC consists of a fractional-N phase-locked loop (PLL)-based frequency synthesizer, a high-bandwidth track-and-hold circuit, and a 10-bit analog-to-digital converter (ADC) to implement a subsampling scheme. The proposed fractional-N PLL-based frequency synthesizer improves the time jitter accumulated in a voltage-controlled oscillator using a fractional frequency divider operated by an eight-phase clock. The bandwidth of the track-and-hold circuit is designed to be 6 GHz, using inductive peaking realized through a source follower. The OCMC samples 49 points over two unit intervals of a high-speed input signal when the frequency multiplication of the frequency synthesizer is 6.125/6. The 10-bit ADC uses the architecture of a pipelined successive approximation register ADC to reduce the power consumption and chip area. The proposed OCMC is implemented with 65-nm CMOS technology and a 1.2 V supply. The 8-Gb/s chip-to-chip interface signal is reconstructed with time and voltage resolutions of 5.1 ps and 1.17 mV, respectively.

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2

A 2.5-Gbps/lane receiver bridge chip, which fully supports the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) camera serial interface (CSI)-2, is proposed for a field-programmable gate array (FPGA)-based frame grabber. The proposed receiver bridge chip converts four-lane high-speed data of scalable low-voltage signaling (SLVS) of the MIPI CSI-2 into 32 low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip. In order to achieve this, each data lane of the proposed receiver bridge chip has a 1-to-8 deserializer including a byte synchronizer. Furthermore, an asynchronous delay line per lane compensates the time skew among the five lanes, including a clock lane. A common-gate level shifter (CGLS) with a continuous-time linear equalizer (CTLE) is proposed to improve the voltage fain and bandwidth of the high-speed receiver. The proposed receiver bridge chip is implemented using a 0.11 μm CMOS process with a 1.2 V supply. The area and power consumption of the proposed receiver bridge chip are 5.29 mm2 and 7.2 me/Gbps/lane, respectively. The proposed CTLE of the high-speed receiver achieves the improved peak-to-peak time jitter of 0.3UI at a data rate of 3.0 Gbps/lane. The FPGA-based frame grabber processes the image or video data supplied by a camera sensor with the MIPI CSI-2 by using the proposed receiver bridge chip.