Young-Chan Jang

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-pm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm 2 and 1.6 W, respectively.

A mixed-mode single-chip motor-drive-specific microcontroller with a 12-bit 125/KS/s ADC

A mixed-mode single-chip motor-driver-specific 32-bit microcontroller was designed and implemented by using a 0.6 /spl mu/m triple-metal CMOS process. The microcontroller chip includes the SPARC-V7 processor as the main CPU, a single-precision floating-point unit, a memory controller, and all the peripheral devices for an AC induction motor drive, including a 12-bit 125 KS/s ADC. The ADC uses a successive approximation algorithm and a folded-array resistor-string DAC to enhance noise immunity and monotonicity. The chip size is 12.1/spl times/11.7 mm/sup 2/, the number of transistors used is around 882,000, and the power consumption is 2.6 W at a supply voltage of 5 V and a clock frequency of 33.3 MHz. The substrate current picked up by a guard ring surrounding the ADC block was measured at different clock frequencies of digital circuits. The correlation between SFDR of ADC and the substrate noise current was demonstrated.

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a 0.13 ㎛ CMOS process. A digital calibration of DC reference voltage is proposed for the 1 st preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the 2 nd preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 ㎽ with a 195 ㎒ 400 ㎷ p-p sine wave input.

An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

An 8-bit 200 MSample/s CMOS folding/interpolating ADC chip was implemented by using a 0.35-/spl mu/m double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published folding/interpolating ADC chips. The delay time of digital encoder block was reduced to 1.3 ns from 2.2 ns by using a DCVSPG-style differential logic. The chip area and the measured power consumption were 1.02 mm/sup 2/ and 120 mW respectively at the supply voltage of 3.3 V.

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8- metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and 620 × 340 μm², respectively.