Pil-Mo Choi

P‐3: Development of CMOS Six Mask and PMOS Five Mask Poly‐Si Architecture with RGB+White Color

We have developed the five mask PMOS and the six mask CMOS process architecture for poly-Si TFT. In order to have a competitive process with that for a-Si TFT, the simple co-planar electrode structure whose data line electrode and pixel electrode are on the same plane was adopted. In addition, RGB + White four color technology were applied to achieve high aperture ratio and transmittance. Using the aforementioned process architecture and four color technology, 2.0 inch qCIF transmissive micro-reflectance (TMR) device was successfully fabricated.

P-39: Development of 5″ Poly-Si Transflective Panel by 7-Mask Process, Operated with P-MOS Circuit

In order to reduce the cost and to have a comparative process with that of a-Si, 7 mask process architecture for Poly-Si was developed in this study. Also, PMOS process architecture is simplifiedand optimized, varying LDDLightly Doped Drain dose, the thickness of gate oxide, typres of ILDInterLayer Dielectric.