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Dive into the research topics where Pilin Liu is active.

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Featured researches published by Pilin Liu.


electronic components and technology conference | 2007

Improved Drop Reliability Performance with Lead Free Solders of Low Ag Content and Their Failure Modes

Hyunchul Kim; Mu Zhang; Chetan Kumar; Daewoong Suh; Pilin Liu; Dongwook Kim; Mayue Xie; Zhiyong Wang

Solder joint reliability of lead free solders (Sn-Ag-Cu) in drop testing has been an issue in mobile and handheld electronics. Since lead free solders have lower drop performance compared with Pb-Sn solders, many efforts have been reported to improve solder joint reliability with various lead free solders. In this study, standard JEDEC drop reliability tests were performed for a CSP (chip scale package) prepared with two different compositions of lead free solders (SAC405 alloy: Sn-4Ag-0.5Cu and SAC105 alloy: Sn-1Ag-0.5Cu). Lead free solders were assembled on substrates with a Au/Ni surface finish. It was seen that SAC 105 alloy solder demonstrated better drop reliability compared with SAC405 alloy solder and failure analysis conducted to understand the differences in failure modes & drop reliability performance.. The fundamental cause of improved drop reliability performance of SAC 105 solders and the advantages of using low Ag content SAC lead free solders for microelectronic devices is discussed. Finally, a finite element model was developed and validated with failure analysis to investigate the high stress concentration distribution and failure mode in solder joints for drop test stress conditions.


electronic components and technology conference | 2016

The Mechanism of Dense Interfacial Voids and Its Impact on Solder Joint Reliability

Pilin Liu; Cyber Lin; Balu Pathangey; Deepak Goyal

SAC 305 solder joints with ENIG and NiPdAu surface finishes are studied. In general, nano voids in Ni2SnP can be only seen in SAC 305/ENIG but not in SAC 305/NiPdAu. However, when trace amount of impurities are present in NiPdAu, very dense nano voids are observed in Ni2SnP. The voids formation mechanism related to interaction of interfacial impurities and vacancy flux towards the interface has been discussed to explain the observations. BGA ball shear test indicates the dense interfacial voids can degrade the solder joint strength dramatically.


electronic components and technology conference | 2015

Key parameters for fast Ni dissolution during electromigration of Sn0.7Cu solder joint

Pilin Liu; Alan Overson; Deepak Goyal

This paper discusses the key parameters for fast Ni dissolution induced electromigration (EM) damage during reliability EM test of Sn0.7Cu solder joints. The results confirm that Sn grain orientation plays the important role on Ni dissolution, which has been reported in literatures. More important, efforts have been made to understand what the key parameters that can modulate the Sn grain orientation distribution of multiple solder joints during solder joint assembly process are. Statistic Electron backscatter diffraction (EBSD) analyses are used to characterize the Sn grain orientation distribution changes. A critical angle between Sn grain c-axis and substrate normal has been defined based on the statistical analyses. It is found that fast Ni dissolution mainly happens when the angle ranged from 0° to 40° during EM reliability testing. With this understanding, the impacts of solidification cooling rate and Cu column dissolution during assembly reflow have been studied. It is concluded that fast cooling rate will increase the chance of Sn grain c-axis align with substrate normal and promote Ni dissolution during EM. On the other hand, Cu column dissolving during reflow can increase the Cu concentration in solder joint and decrease the possibility of c-axis along with substrate normal. Besides Sn grain orientation, it is interesting to find that solder joint height can also impact Ni dissolution during EM. Longer solder joint height can induce faster Ni dissolution.


electronic components and technology conference | 2017

Failure Mechanism and Kinetics Studies of Electroless Ni-P Dissolution in Pb-Free Solder Joints under Electromigration

Pilin Liu; Chaitra Chavali; Alan Overson; Deepak Goyal

Electromigration (EM) of Pb-free SnCu solder joints with NiPdAu surface finishes are studied. The failure mechanism and kinetics of electroless Ni-P dissolution under EM are discussed in detail. Under EM, depends on the Sn grain orientations, Ni atoms in Ni-P plating can be quickly consumed and the entire Ni-P plating can be transformed to P rich Ni3P. The volume shrinkage caused by this reaction can induce the Ni3P/Cu separation or accelerate the voids nucleation between IMC/solder. Two interesting phenomena were observed in kinetics studies of Ni dissolution: (1) the existence of long incubation time before the onset of Ni dissolution, (2) Depending on Sn grain orientations, Ni dissolution rate varies dramatically. The current density exponent n (shown in Blacks law) for fast Ni dissolution is much larger than that for slow Ni dissolution.


Journal of Electronic Materials | 2017

Root Cause Investigation of Lead-Free Solder Joint Interfacial Failures After Multiple Reflows

Yan Li; Olen Hatch; Pilin Liu; Deepak Goyal

Solder joint interconnects in three-dimensional (3D) packages with package stacking configurations typically must undergo multiple reflow cycles during the assembly process. In this work, interfacial open joint failures between the bulk solder and the intermetallic compound (IMC) layer were found in Sn–Ag–Cu (SAC) solder joints connecting a small package to a large package after multiple reflow reliability tests. Systematic progressive 3D x-ray computed tomography experiments were performed on both incoming and assembled parts to reveal the initiation and evolution of the open failures in the same solder joints before and after the reliability tests. Characterization studies, including focused ion beam cross-sections, scanning electron microscopy, and energy-dispersive x-ray spectroscopy, were conducted to determine the correlation between IMC phase transformation and failure initiation in the solder joints. A comprehensive failure mechanism, along with solution paths for the solder joint interfacial failures after multiple reflow cycles, is discussed in detail.


Archive | 2016

Symmetric and Asymmetric Double Cantilever Beam Methods for Interfacial Adhesion Strength Measurement in Electronic Packaging

Tsgereda Alazar; Santosh Sankarasubramanian; Sivakumar Yagnamurthy; Kyle Yazzie; Pilin Liu; Pramod Malatkar

This paper discusses Double Cantilever Beam (DCB) test methods that were developed for characterizing adhesion strength of several critical interfaces in advanced microelectronic packaging. Those interfaces include silicon-epoxy underfill and solder resist-epoxy underfill. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon-underfill samples and cracking of solder resist films in solder resist-underfill samples. Additionally, asymmetric DCB samples (i.e., different cantilever beam thickness on top compared to the bottom) were found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Several case studies using DCB for material selection and assembly process optimization are also discussed. Furthermore, fractography results from SEM examination of the fractured surfaces are also presented for better understanding of the failure mode.


electronic components and technology conference | 2015

A hybrid approach to characterize adhesion strength of interfaces in an organic substrate

Bharat Penmecha; Tsgereda Alazar; Dilan Seneviratne; Pilin Liu; Pramod Malatkar

Organic substrates used in flip-chip packaging consist of multiple layers of alternating dielectric and copper layers built around a glass-fiber Core material. These materials have widely different mechanical properties which makes the interfaces between these layers susceptible to delamination. As a result, adhesion between them is a critical mechanical property governing the reliability performance of substrate packages. Developing metrologies which can quantify the adhesive properties of an interface is an essential component of substrate process development. Peel-test is a popular metrology used to characterize adhesion of a film deposited over an underlying material. When inelastic materials are involved (like copper in this case) the peel-force measured is a convoluted function of thickness of the film, mechanical properties of the materials involved, test speed, and the true interfacial properties. Due to this, a clear understanding of the true adhesion strength based solely on experimentation is not possible. Focus of this publication is to utilize mechanical modeling (Finite element analysis) coupled with experimentation to extract the key adhesion metric - the interface fracture energy (Gc). We present our analysis in the case of copper films electroplated on a desmeared dielectric layer. We discuss in detail our findings on the effect of various parameters - peel film thickness, peel velocity, film width on the peel force, from experiments, sample fractography and modeling.


electronic components and technology conference | 2015

The mechanism and kinetic study of void migration in Cu vias under current flow by 3D X-ray computed tomography

Yan Li; Luhua Xu; Pilin Liu; Balu Pathangey; Mario Pacheco; Mohammad M. Hossain; Liang Hu; Rajen Dias; Deepak Goyal

Miniaturization and portability of consumer electronics is driving the substrate technology to enable packages with higher circuit density, smaller size, and lower Z height. Cu vias with large aspect ratio are being used for these next generation substrate technologies. Due to the relatively large aspect ratio of the Cu vias, voids could form during the electrolytic Cu filling process. To understand the void behavior under current flow, samples are subjected to high current at elevated temperatures. 3D X-ray computed tomography is used to characterize these voids in Cu vias before and during the test at intermediate readouts. These studies find that the voids accumulate and migrate preferentially to the applied bias polarity. The hypothesis of the void movement under current flow is discussed and the kinetics of the void migration is proposed with the estimations of activation energy and current density exponent.


Materials Science and Engineering A-structural Materials Properties Microstructure and Processing | 2007

Effects of Ag content on fracture resistance of Sn–Ag–Cu lead-free solders under high-strain rate conditions

Daewoong Suh; Dong W. Kim; Pilin Liu; Hyunchul Kim; Jessica Weninger; Chetan Kumar; Aparna Prasad; Brian W. Grimsley; Hazel B. Tejada


Journal of Electronic Materials | 2004

Effect of cooling rate on microstructure and shear strength of pure Sn, Sn-0.7Cu, Sn-3.5Ag, and Sn-37Pb solders

James G. Maveety; Pilin Liu; J. Vijayen; Fay Hua; E. A. Sanchez

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