Pramod Malatkar

Vibration Testing and Analysis of Ball Grid Array Package Solder Joints

A methodology to characterize and predict fatigue failure of BGA package solder joints under vibration loading is presented. The results show that the board strain versus number-of-cycles-to-failure (or E-N) curve has a linear trend with little scatter in data points, similar to that of a classical fatigue theory using cyclic stress versus number-of-cycles-to-failure (or S-N) curves. Using finite element analysis (FEA), the solder joint stress was shown to be linearly correlated to the board strain. Therefore, board strain can indeed be used as an optimum engineering metric to study the fatigue of ball grid array (BGA) solder joints. In addition, the E-N curve approach was shown to be applicable to cyclic bend and cyclic shock loading conditions as well. The E-N curves of lead-free and leaded solder systems also have been generated and compared to demonstrate that the lead-free system has a better high-cycle fatigue performance. In addition, a fatigue-life prediction methodology based on the Miners cumulative damage theory is proposed. The effectiveness of this methodology was demonstrated with promising results through random vibration testing of actual motherboards. Finally, a novel approach to study solder joint reliability (SJR) under vibration loading at the system level, using a fatigue curve generated at the component level is presented.

Pitfalls an engineer needs to be aware of during vibration testing

In the electronic industry, there is currently a renewed interest in the study of the failure of BGA package and socket solder joints under mechanical stressing, specifically shock and vibration. This means that an analyst now needs to know the proper modeling and test procedures to use in order to better tackle the problem of solder joint reliability under shock and vibration loading. In this paper, an effort has been made to collate the best known methods associated with vibration testing of electronic components mounted on printed circuit boards

A mechanical fatigue assessment methodology to study solder joint reliability

This paper presents a unified mechanical fatigue assessment methodology that characterizes and predicts the fatigue life performance of electronic components. It involves establishing the relationship between a solder ball damage metric and the fatigue cycles-to-failure. With the proposal of board strain as a metric, single BGA component test boards are used to produce a fatigue characterization curve - the E-N curve. The methodology was initially established using high cycle fatigue but later extended to the lower cycle fatigue region to give a complete picture of the characteristics. The methodology has been validated by predicting fatigue failure of a system board under random vibration using the rainflow-counting algorithm and Palmgren-Miners damage accumulation. Discussion on board design implications and features to improve fatigue performance are presented. Furthermore, a case study with the methodology used to assess the mechanical integrity risk of two mobile devices is shared. The sensitivity of the methodology towards various board and package attributes is also demonstrated.

Contact Pressure and Load Measurement Techniques for Applications in Semiconductor Packaging

Semiconductor packages undergo mechanical loading at various stages of the manufacturing, assembly and test process. Also, during the assembly of the thermal enabling solution in a system environment, mechanical loads are applied to ensure contact of the thermal solution. These loads can be static and/or dynamic in nature, applied over a short or long periods of time. It is important to characterize these applied loads and the resulting contact pressure. However, the measurement of the contact pressure at the interface is complex and requires special techniques without altering the mechanical boundary conditions or the state of stress. In this paper, some of the existing methods used to measure the in-situ load and pressure distribution will be discussed with special attention provided to methods including: pressure-sensitive paper, piezo-resistive based pressure films, and load cells. We will also discuss the applications of these approaches in semiconductor packaging. In the pressure paper technique, a thin film containing microbeads is placed between the interfaces of interest. These microbeads contain colored ink and rupture when a threshold pressure is applied. The intensity and location of the ink provides the magnitude of pressure and its distribution. While these are inexpensive and easy to use, they are single-use and fail to provide real time data. Another method is to use a thin piezo-resistive sensor. While this technique can provide real-time pressure measurements, it is expensive and comes with additional challenges such as hysteresis, aging, and history-dependent response due to the inherent nature of materials used in the sensor. As a result, obtaining accurate and reproducible measurements is quite challenging. In this paper, we describe an experimental method to quantify the challenges and present an approach to mitigate them to achieve highly accurate and repeatable measurements. Lastly, embedded button load cells or dynamic load cells are also used to study mechanical loads a package is experiencing, but they are bulky and hence hard to use especially when space is limited.

Symmetric and Asymmetric Double Cantilever Beam Methods for Interfacial Adhesion Strength Measurement in Electronic Packaging

This paper discusses Double Cantilever Beam (DCB) test methods that were developed for characterizing adhesion strength of several critical interfaces in advanced microelectronic packaging. Those interfaces include silicon-epoxy underfill and solder resist-epoxy underfill. A unique sample preparation technique was developed for DCB testing of each interface in order to avoid the testing challenges specific to that interface—for example, silicon cracking and voiding in silicon-underfill samples and cracking of solder resist films in solder resist-underfill samples. Additionally, asymmetric DCB samples (i.e., different cantilever beam thickness on top compared to the bottom) were found to be more effective in maintaining the crack at the interface of interest and in reducing the occurrence of cohesive cracking when compared to symmetric DCB samples. Several case studies using DCB for material selection and assembly process optimization are also discussed. Furthermore, fractography results from SEM examination of the fractured surfaces are also presented for better understanding of the failure mode.

A hybrid approach to characterize adhesion strength of interfaces in an organic substrate

Organic substrates used in flip-chip packaging consist of multiple layers of alternating dielectric and copper layers built around a glass-fiber Core material. These materials have widely different mechanical properties which makes the interfaces between these layers susceptible to delamination. As a result, adhesion between them is a critical mechanical property governing the reliability performance of substrate packages. Developing metrologies which can quantify the adhesive properties of an interface is an essential component of substrate process development. Peel-test is a popular metrology used to characterize adhesion of a film deposited over an underlying material. When inelastic materials are involved (like copper in this case) the peel-force measured is a convoluted function of thickness of the film, mechanical properties of the materials involved, test speed, and the true interfacial properties. Due to this, a clear understanding of the true adhesion strength based solely on experimentation is not possible. Focus of this publication is to utilize mechanical modeling (Finite element analysis) coupled with experimentation to extract the key adhesion metric - the interface fracture energy (Gc). We present our analysis in the case of copper films electroplated on a desmeared dielectric layer. We discuss in detail our findings on the effect of various parameters - peel film thickness, peel velocity, film width on the peel force, from experiments, sample fractography and modeling.

On the mechanical fatigue study of second-level interconnects using the E-N curve approach

The authors presented, in an earlier paper, an unified component-level approach for characterizing fatigue behavior of BGA package solder joints under Vibration, Cyclic Bend and Cyclic Shock loading conditions [1,2]. The approach involves creating a board strain versus number of cycles-to- failure curve, also known as E-N curve, using data collected from the three tests. For BGA packages used in mobile notebooks, the authors showed that all of the data points, for a given failure mode, fall along a straight line - similar to the classical metal fatigue (S-N) curves. In this paper, that effort is extended to other market segments, with varying board thickness, and component types. Specifically, applicability of the E-N curve approach to CPU sockets and small-form- factor (SFF) packages used in mobile internet devices and the effect of board thickness on the mechanical fatigue performance are explored. The study was limited to lead-free solders, but the learnings can be applied to leaded solder systems.