Pingqiang Zhou

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits

Thermal issues are a primary concern in the three-dimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic optimization techniques, hampering performance and scalability when used for 3D floorplanning. In this work, we propose and evaluate a scalable, temperature-aware, force-directed fioorplanner called 3D-STAF. Force-directed techniques, although efficient at reacting to physical information such as temperature gradients, must eventually eliminate overlap. This can cause significant displacement when used for heterogeneous blocks. To smooth the transition from an unconstrained 3D placement to a legalized, layer-assigned floorplan, we propose a three-stage force-directed optimization flow combined with new legalization techniques that eliminate white spaces and block overlapping during multi-layer floorplanning. A temperature-dependent leakage model is used within 3D-STAF to permit optimization based on the feedback loop connecting thermal profile and leakage power consumption. 3D-STAF has good performance that scales well for large problem instances. Compared to recently published 3D floorplanning work, 3D-STAF improves the area by 6%, wire length by 16%, via count by 22%, peak temperature by 6% while running nearly 4times faster on average.

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network

In this paper, we explore the design of on-chip switched-capacitor (SC) DC-DC converters in the context of multicore processors, using an accurate power grid simulator. Results show that distributed design of SC converters can reduce the IR drop by up to 74% compared to the lumped design, with improved supply voltage. We also demonstrate the usage of SC converters for multi-domain power supply.

Application-specific 3D Network-on-Chip design using simulated allocation

Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

Thermal and Power Delivery Challenges in 3D ICs

Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

NoC frequency scaling with flexible-pipeline routers

Voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. We propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network frequency and save network energy, without significant performance degradation. Furthermore, we demonstrate the use of simple performance metrics to determine the optimal operation frequency, considering the energy/performance impact on all aspects of the system — the cores, the caches and the interconnection network.

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems

NoCs are an integral part of modern multicore processors, they must continuously support high-throughput low-latency on-chip data communication under a stringent energy budget when system size scales up. Heterogeneous multicore systems further push the limit of NoC design by integrating cores with diverse performance requirements onto the same die. Traditional packet-switched NoCs, which have the flexibility of connecting diverse computation and storage devices, are facing great challenges to meet the performance requirements within the energy budget due to latency and energy consumption associated with buffering and routing at each router. In this paper, we take advantage of the diversity in performance requirements of on-chip heterogeneous computing devices by designing, implementing, and evaluating a hybrid-switched network that allows the packet-switched and circuit-switched messages to share the same communication fabric by partitioning the network through time-division multiplexing (TDM). In the proposed hybrid-switched network, circuit-switched paths are established along frequently communicating nodes. Our experiments show that utilizing these paths can improve system performance by reducing communication latency and alleviating network congestion. Furthermore, better energy efficiency is achieved by reducing buffering in routers and in turn enabling aggressive power gating.

Distributed On-Chip Switched-Capacitor DC–DC Converters Supporting DVFS in Multicore Systems

Dynamic voltage and frequency scaling (DVFS) is a powerful technique to reduce power consumption in a chip multiprocessor. To support DVFS in the multicore power delivery network, we integrate on-chip switched-capacitor (SC) dc-dc converters that can work with multiple conversion ratios to provide varying levels of Vdd supplies. We study the application of such SC converters in multicore chips by simulation. Our results show that distributed SC converters can significantly reduce the voltage droop seen by the local core loads by providing better localized power regulation. Considering the fact that the current distribution in a multicore chip is unbalanced, we further develop computer-aided design techniques to automate the design (size) and distribution (number and location) of these SC converters, using the efficiency of the whole power delivery system as the optimization metric. This is a major concern, but has not been addressed at the system level in prior research. We develop models for the power loss of such a system as a function of size and distribution of the SC converters, then propose an approach to optimize the SC converters to maximize the efficiency of the system, while considering all the possible conversion ratios an SC converter can work with. We verify the accuracy of our models for the power loss in the power delivery system, and demonstrate the efficiency of our techniques to optimize the SC converters on both homogenous and heterogenous multicore chips.