Piotr Kmon

Energy Efficient Low-Noise Multichannel Neural Amplifier in Submicron CMOS Process

This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channels input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 μW of power, while its input referred noise is equal to 4.4 μV resulting in NEF equal to 4.1.

Design and Tests of the Vertically Integrated Photon Imaging Chip

The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.

VIPIC IC — Design and test aspects of the 3D pixel chip

We report on the design of the VIPIC IC (Vertically Integrated Pixel Imaging Chip) designed for X-ray Photon Correlation Spectroscopy (XPCS) experiments by FNAL in collaboration with AGH-UST. The VIPIC chip is a prototype matrix with 64 × 64 pixels with 80 μm × 80 μm pixel size and consists of two layers: analog and digital. The single analog pixel cell consists of a charge sensitive amplifier, a shaper, a single current discriminator and trim DACs. The simulated gain is 52 μV/e⁻, the noise ENC < 150 e⁻ rms (with C<inf>det</inf>= 100 fF) and the peaking time t<inf>p</inf> < 250 ns. The power consumption is 25 μW/pixel in the analog part. The digital layer of the VIPIC integrated circuit is divided into 16 readout groups of pixels read out in parallel via separate serial ports with nominal frequency of the 100 MHz clock using the LVDS standard. The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixels only) allows a dead-time free readout.

A bidirectional 64-channel neurochip for recording and stimulation neural network activity

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DACs. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

Design and measurements of 64-channel ASIC for neural signal recording

This paper presents the design and measurements of a low noise multi-channel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and was fabricated in CMOS 0.18 µm technology. A single readout channel is built of an AC coupling circuit at the input, a low noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and matching performance with the possibility of cut-off frequencies tuning. The low cut-off frequency can be tuned in the 1 Hz–60 Hz range and the high cut-off frequency can be tuned in the 3.5 kHz–15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 µW the equivalent input noise is in the range from 6 µV–11 µV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency is on the same level. The chip occupies 5×2.3 mm2 of silicon area.

Results of tests of three-dimensionally integrated chips bonded to sensors

The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80 μm) were also bonded to silicon pixelated sensors (with a pixel pitch of 100 μm) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39 e- and 70 e- , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52 μV/e- as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational.

23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e − rms, 19 e − rms offset spread and 3% rms gain spread

We report on the novel method of an in-pixel offset and gain correction for implementation in multichannel hybrid detector readout circuits. A prototype ASIC consisting of 23552 square shaped pixels of 75 μm pitch was designed and fabricated in CMOS 130 nm technology. Each pixel containing charge sensitive amplifier, shaper, discriminator, correction circuits and two 14-bit counters has an equivalent noise charge of 89 e- rms and dissipates only 25 μW. Tests prove its exceptional uniformity with an offset spread of 19e- rms and the gain spread of only 3%, rms what is good enough for color X-Ray imaging. The paper presents the architecture of the ASIC, a transistor level novel schematic of key blocks used for offset and gain trimming, the testing procedure and its results.

An Effective Multilevel Offset Correction Technique for Single Photon Counting Pixel Detectors

We report on a novel technique of an in-pixel multilevel offset correction to be used in hybrid pixel detector readout circuits operating in a single photon counting mode. This technique was implemented in a prototype integrated circuit consisting of 23,552 square shaped pixels of 75 μm pitch, which was designed and manufactured in CMOS 130 nm technology. Each pixel contains a charge sensitive amplifier, shaper, two discriminators, two 14-bit counters and a block for multilevel offset correction. The effective gain and offset are controlled individually in each pixel. The measurement results prove very good uniformity of the prototype integrated circuit with an offset spread of only 7e- rms and a gain spread of 2.5%.

Low-power low-noise versatile amplifier for neural signal recording

We present the design and simulation of the neural recording amplifier in the CMOS 180 nm technology. Amplifier is capable of recording signals from mHz range up to kHz range while rejecting large DC offset generated on the electrode-electrolyte interface. Its band may be control to span over all interesting biopotential signals (low cutoff frequency from 73 mHz to 125 Hz while the upper cutoff frequency from 1.85 kHz to 16.5 kHz). Due to its low input referred noise 4.5 muV (integrated from 1 mHz to 100 kHz), low power consumption 28 muW per one channel, small occupied area 0.094 mm2 and small spreads of its main parameters designed amplifier is a good candidate for multichannel neural recording system.