Marcel Trimpl

Vertically Integrated Circuits at Fermilab

The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

Design and Tests of the Vertically Integrated Photon Imaging Chip

The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.

A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider

Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 × 20 ¿m2 pixels, laid out in an array of 64 × 64 elements and was fabricated in a 3-tier 0.18 ¿m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout.

Analysis of full charge reconstruction algorithms for X-ray pixelated detectors

Existence of the natural diffusive spread of charge carriers on the course of their drift towards collecting electrodes in planar, segmented detectors results in a division of the original cloud of carriers between neighboring channels. This paper presents the analysis of algorithms, implementable with reasonable circuit resources, whose task is to prevent degradation of the detective quantum efficiency in highly granular, digital pixel detectors. The immediate motivation of the work is a photon science application requesting simultaneous timing spectroscopy and 2D position sensitivity. Leading edge discrimination, provided it can be freed from uncertainties associated with the charge sharing, is used for timing the events. Analyzed solutions can naturally be extended to the amplitude spectroscopy with pixel detectors

VIPIC IC — Design and test aspects of the 3D pixel chip

We report on the design of the VIPIC IC (Vertically Integrated Pixel Imaging Chip) designed for X-ray Photon Correlation Spectroscopy (XPCS) experiments by FNAL in collaboration with AGH-UST. The VIPIC chip is a prototype matrix with 64 × 64 pixels with 80 μm × 80 μm pixel size and consists of two layers: analog and digital. The single analog pixel cell consists of a charge sensitive amplifier, a shaper, a single current discriminator and trim DACs. The simulated gain is 52 μV/e⁻, the noise ENC < 150 e⁻ rms (with C<inf>det</inf>= 100 fF) and the peaking time t<inf>p</inf> < 250 ns. The power consumption is 25 μW/pixel in the analog part. The digital layer of the VIPIC integrated circuit is divided into 16 readout groups of pixels read out in parallel via separate serial ports with nominal frequency of the 100 MHz clock using the LVDS standard. The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixels only) allows a dead-time free readout.

Results of tests of three-dimensionally integrated chips bonded to sensors

The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80 μm) were also bonded to silicon pixelated sensors (with a pixel pitch of 100 μm) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39 e- and 70 e- , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52 μV/e- as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational.

Vertically integrated circuits at fermilab

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

An on-chip charge cluster reconstruction technique in the miniVIPIC pixel readout chip for X-ray counting and timing

An on-chip algorithm for the allocation of a hit to a single pixel in the presence of charge sharing in a highly segmented pixel detector is presented. It has been developed to advance pixel detector technology for experiments with X-ray beams at a synchrotron facility. Its key elements are: activation of groups of pixels (neighborhood_active), comparisons of peak amplitudes within the active neighborhood, virtual pixels that recover composite signals, ability to create event driven strobes to control comparisons of fractional signals between neighboring pixels and finally latching of the results of these comparisons. The miniVIPIC prototype was designed in a 130 nm process, as a proof of feasibility. The chip contains an array of 32×32 100×100 μm2 pixels. Analog and digital signals are exchanged between pixels, forming an extensive inter-pixel connection grid, whose routing to minimize parasistics, represented the major challenge. The design details of the chip are provided.

First Three-Dimensionally Integrated Chip for Photon Science

We report on the results from testing of the first three-dimensionally integrated readout chip for pixel detectors, which application is in X-ray Photon Correlation Spectroscopy (XPCS) experiments on light sources. The chip was designed in the 130nm Tezzaron/GF process as a two-tier device with effectively 12 metal layers of routing. It counts about 1,700 transistors in total in 80x80um^2 pixels. The chip explores broadly the benefits of the 3D integration for pixel detectors, like full separation of analog and digital parts by placing them accordingly on distinct tiers, improved power distribution by using back-side located pads and almost no periphery for achieving 4-side buttability. VIPIC1, as that is the name of the chip, was designed by FNAL in collaboration with AGH-UST. The tests are underway on the singulated devices from the first successfully bonded wafer pairs. Correct operation of all components tested so far was observed. This includes: full sparsified readout that is based on a priority encoder, pipelined inpixel hit acquisition with two alternately switched event counters, programming interfaces for permanent setting and disabling of a pixel and acquisition of hits from the analog part with full sensitivity to settings of discriminator thresholds. Current work is focused on measurements of pixel-to-pixel deterministic offsets, electronic noise and calibration of gain using injection of test charges. Every pixel features multiple connections across two-tier boundary. No faults were observed in the 3D bonding interface as well as the connectivity carried by through silicon vias was observed to be achieved on all dies that were qualified as good after wafer thinning. Despite of the long waiting for the first 3D chips, the test results are encouraging for the threedimensional integration technology as a cost and performance efficient alternative to the aggressive node down scaling.

SOI detector with drift field due to majority carrier flow — An alternative to biasing in depletion

This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 ×2.5mm2 large detector array with 20 μm and 40 μm pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes, will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.