Piotr Sapiecha

FUNCTIONAL DECOMPOSITION AND ITS APPLICATIONS IN MACHINE LEARNING AND NEURAL NETWORKS

In this paper, we will begin with an overview of functional decomposition algorithms based on different graph coloring heuristics. We will then discuss the applications of decomposition strategy for the computer aided design of digital circuits and for the supervised learning of neural networks. While decomposition was used successfully in logic synthesis for several years, its application in the area of neural networks is a novel and promising approach. The computer experiments will show significant benefits in mini mization of silicon space required for digital circuit implementation as well as in reduction of training time for neural networks.

Building Dependable Intrusion Prevention Systems

Intrusion prevention systems (IPSs) have become widely recognized as a powerful tool and an important element of IT security safeguards. Essential to every network intrusion prevention system is the ability to search through packets and identify patterns that match known attacks. Resource- and time-efficient string matching algorithms are therefore important for identifying these packets at the line rate. Recently these systems have become a target of attacks - the example is the infamous Witty worm. The devices which use algorithms with low worst-case performance could be a target of algorithmic complexity attacks. For example, poorly prepared hash tables can degenerate to linked lists with carefully chosen input. An attacker can effectively compute an input data that will diminish the device throughput. This can lead to denial of service attacks, which are very dangerous for networks and computational environments. In this article new hardware implementation architecture of the Karp-Rabin algorithm was introduced. The result is a software, which generates a pattern matching module that could be easily used to create intrusion prevention systems implemented in reconfigurable hardware. The prepared module matches the subset of the Snort IPS signatures achieving throughput of over 2 Gbps and have the worst-case performance similar to the best-case one. This means that the presented implementation architecture is immune to algorithmic complexity attacks

Approximation Algorithm for the Argument Reduction Problem

This paper proposes a new method of solving the argument reduction problem. Our method is different to the classical approach using the greedy algorithm, independently invented by Lovasz, Johnson, and Chvatal. However, sometimes the classical method does not produce minimal sets in the sense of cardinality. According to the results of computer tests, better results can be achieved by application of our method in combination with the classical method. Therefore, improvements are found in the quality of solutions when it is applied as a post-processing method.

Decomposition and Argument Reduction of Neural Networks

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors’ experiments, in some cases, argument reduction, makes the learning process harder.

Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis

This paper shows that the problem of decomposing a finite function f(A, B) into the form h(g(A),B), where g is a Boolean function, can be resolved in polynomial time, with respect to the size of the problem. It is also shown that omission of the characteristic of the g function can significantly complicate the problem. Such a general problem belongs to the NP-hard class of problems. The work shows how the problem of decomposition of a finite function can be reduced to the problem of coloring the vertices of a graph. It is also shown that the problem of decomposition of relations can be reduced to coloring the vertices of their hypergraphs. In order to prove the validity of the theorems, combinatory properties of Helly are used.

Implementation of Karp-Rabin string matching algorithm in reconfigurable hardware for network intrusion prevention system

Intrusion Prevention Systems (IPSs) have become widely recognized as a powerful tool and an important element of IT security safeguards. The essential feature of network IPSs is searching through network packets and matching multiple strings, that are fingerprints of known attacks. String matching is highly resource consuming and also the most significant bottleneck of IPSs. In this article an extension of the classical Karp-Rabin algorithm and its implementation architectures were examined. The result is a software, which generates a source code of a string matching module in hardware description language, that could be easily used to create an Intrusion Prevention System implemented in reconfigurable hardware. The prepared module matches the complete set of Snort IPS signatures achieving throughput of over 2 Gbps on an Altera Stratix I1 evaluation board. The most significant advantage of the proposed architecture is that the update of the patterns database does not require reconfiguration of the circuitry.

Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

The ASIC designs are growing larger everyday. It is very hard to simulate these designs because the simulation time has risen tremendously. An alternate solution is to partition the large design into modules and perform incremental simulation. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of large ASICs. On the other hand, since the introduction of FPGAs, they have been playing an important role in ASIC design cycle. But due to very large size of todays ASIC designs (millions of gates) compared to FPGAs, it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. This paper takes a large RTL design of an ASIC into consideration, analyzes the size of each module in terms of number of CLBs, I/Os, flip-flops, latches and applies the algorithm to partition it automatically into minimum number of FPGAs.

Towards model-based anomaly detection in network communication protocols

Over the last few years many techniques have been applied to find and mitigate vulnerabilities, misuses, cyber-attacks and other cyber-security flaws. One of the approaches, which we consider in this paper, is a model-based technique applied to network communication protocols. This idea is not brand new, and model-based techniques have been successfully used to verify and validate the standard models of communication protocols. However, the implementation of network protocols varies from one system to another, and in many cases they miss standards or recommendations. Attackers know these flaws very often and try to use them before everybody else finds them, what can be called “zero-day exploit of communication protocol.” To address this issue, a combination of the best features of model-based and anomaly detection techniques could be applied. Treating discovered anomalies as a signature of a cyber-attack or any other malicious activity and focusing on the investigation of them could significantly increase the success rate of the defense against them. In this paper we considered some significant inputs from the research community to model-based anomaly detection in network communication protocols. Then we prepared a synthetic brief of the theories and methods for modelling network protocols as state-machines. Next we examined the application of it in a cyber-security area. Finally we proposed some key directions that actual research should follow to bring some breakthrough results as soon as possible.

Solving the k-centre problem as a method for supporting the Park and Ride facilities location decision

In this article we analyze the problem of optimal location of transportation hubs in Warsaw, namely the Park and Ride location problem (P&RP).We take into account the expected travel time using public transport between particular points of the trip. In the currently existing P&R system we have 14 hub locations, and in this case the maximum travel time exceeds 50 minutes. The P&R problem can be reduced to the centers location problem (in our particular approach - the dominating set problem, DS), which is an NP hard problem. In order to determine the optimal locations for P&R two methods: the greedy and the tabu search algorithms were chosen and implemented. According to the computational experiments for the travel time restriction to 50 minutes, we obtain the DS composed of 3 hubs, in contrast to the existing 14 elements. The analysis of the P&R location in time domain is presented in this article in the context of further development of the Warsaw public transportation network, which seems to be interesting.

Hardware Implementation of Rainbow Tables Generation for Hash Function Cryptanalysis

Nowadays programmable logic structures are commonly used in cryptology. FPGA implementations of cryptographic and cryptanalytic algorithms combine advantages of an ASIC and a software, offering both great data processing speed and flexibility. In this paper, we present the design and implementation of a system for rapid rainbow tables’ generation. Rainbow tables are commonly used for cryptanalysis of hash functions. The presented approach shows that proposed method may compete with CPU-based approaches when performance is considered, as well as computational complexity, while maintaining low level of programmable structures’ logic element utilization.