Tadeusz Łuba

An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures

The functional decomposition of binary and multi-valued discrete functions and relations has been gaining more and more recognition. It has important applications in many fields of modern digital system engineering, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, data bases, data mining etc. However, its practical usefulness for very complex systems has been limited by the lack of an effective and efficient method for selecting the appropriate input supports for sub-systems. In this paper, a new effective and efficient functional decomposition method is proposed and discussed. This method is based on applying information relationship measures to input support selection. Using information relationship measures allows us to reduce the search space to a manageable size while retaining high-quality solutions in the reduced space. Experimental results demonstrate that the proposed method is able to construct optimal or near-optimal supports very efficiently, even for large systems. It is many times faster than the systematic support selection method, but delivers results of comparable quality.

Multi-level logic synthesis based on decomposition

Abstract An effective logic synthesis procedure based on the functional decomposition of a Boolean function is presented. A distinctive feature of the proposed method is that the decomposition is carried out as the first step of the synthesis process. The presented procedure is suitable for various implementation styles, including PLAs, PLDs and FPGAs. The results of the benchmark experiments presented show that, in several cases, the method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Fast Algorithm of Attribute Reduction Based on the Complementation of Boolean Function

In this chapter we propose a new method of solving the attribute reduction problem. Our method is different to the classical approach using the so-called discernibility function and its CNF into DNF transformation. We have proved that the problem is equivalent to very efficient unate complementation algorithm. That is why we propose new algorithm based on recursive execution of the procedure, which at every step of recursion selects the splitting variable and then calculates the cofactors with respect to the selected variables (Shannon expansion procedure). The recursion continues until at each leaf of the recursion tree the easily computable rules for complement process can be applied. The recursion process creates a binary tree so that the final result is obtained merging the results in the subtrees. The final matrix represents all the minimal reducts of a decision table or all the minimal dependence sets of input variables, respectively. According to the results of computer tests, better results can be achieved by application of our method in combination with the classical method.

5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs

The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

Energy characteristic of a processor allocator and a network-on-chip

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

Rough Sets and Some Aspects of Logic Synthesis

This paper is dedicated to two seemingly different problems. The first one concerns information systems theory and the second one is connected to logic synthesis methods. The common aspect in considering these problems together is the important task of the economic representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction as well as functional decomposition of decision/truth tables is presented. In the latter case a new technique is suggested, which decomposes the original decision/ truth table into an equivalent set of subtables. Using manipulations based on both rough sets and Boolean algebra theory, the decision table is reduced and decomposed so as to get an efficient implementation.

The Influence of Functional Decomposition on Modern Digital Design Process

General functional decomposition has been gaining more and more importance in recent years. Though it is mainly perceived as a method of logic synthesis for the implementation of Boolean functions into FPGA-based architectures, it has found applications in many other fields of modern engineering and science. In this paper, an application of balanced functional decomposition in different tasks of modern digital designing is presented. The experimental results prove that functional decomposition as a method of synthesis can help implementing circuits in CPLD/FPGA architectures. It can also be efficiently used as a method for implementing FSMs in FPGAs with Embedded ROM Memory Blocks.

On memory capacity to implement logic functions

The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMB). Existing tools/compilers treat ROM modules described in HDLs as indivisible entities and in consequence do not ensure effective utilization of the possibilities provided by such modules. In order to address this problem effectively we propose applying functional decomposition. The main contribution is based on the use of r-admissibility measure to guide decomposition structures for ROM-based synthesis.

A notion of r-admissibility and its application in logic synthesis

Abstract This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.