Tadeusz Luba

Decomposition of multiple-valued functions

This paper presents a generalized method for decomposition of multiple-valued functions. The main reason for using the described method is efficient implementation of logic circuits as well as effective representation of data in information systems. In logic synthesis, the method reduces the demand for silicon space required to implement designs. It is shown that the decomposition technique leads to additional compressing capabilities in PLA implementations. Another very promising area of application of decomposition is its effective representation of data in information systems, data bases and in other applications of information storing systems.

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Balanced multilevel decomposition and its applications in FPGA-based synthesis

A general decomposition concept is presented in this paper. The main strategy behind the presented Multilevel Decomposition Method is striking a balance between serial decomposition and parallel decomposition. The method is applicable to a variety of Field Programmable Gate Arrays and allows trading-off area and delay of final implementation. The results prove that the method is efficient and does not suffer from its generality.

Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition

General functional decomposition has important applications in many fields of modern engineering and science. However, its practical usefulness for very complex systems is limited by the lack of an effective and efficient method for the construction of high quality sub-systems. One of the three basic problems of sub-system construction is the choice of an appropriate multi-valued sub-function to be computed by a certain sub-system. In this paper we show that the number of values of the sub-function is the decisive factor in sub-function selection. It shows a very strong positive correlation with both the number of logic blocks and the number of logic levels in the decomposition network, i.e. with the cost and delay of the network. This is a very important result from the practical viewpoint, because its exploitation enables efficient construction of high-quality multi-level circuits, by selection of a sub-function with the minimum possible number of values at each decomposition step. This result also gives a link for the input support selection for sub-systems. The selected input support should enable construction of a sub-function with the minimum possible number of values.

Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping

We present a new theory of non-disjoint serial decomposition. We also present our new decomposition tool DEMAIN. The decomposition approach implemented in DEMAIN relies on: a partition-based representation of Boolean functions; and an effective balanced decomposition strategy that switches between the parallel and non-disjoint serial decomposition. In consequence, we applied the non-disjoint serial decomposition and parallel decomposition for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation.

Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGAs and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLDs to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGAs has been developed. Preliminary experimental results are extremely encouraging.

Evolutionary multi-level network synthesis in given design style

This paper extends the technique of evolutionary network design. We study an evolutionary network design strategy from the position of design style. A hypothesis under investigation is that the uncertainty of a total search space (the space of all possible network solutions) through evolutionary network design is removed faster if this space is partitioned into subspaces. This idea has been realized through a parallel window-based scanning of these subspaces. Such a window is determined by the parameters of a multi-level network architecture in a given design style. Our approach allows to synthesize networks with more than two hundred quaternary gates. Moreover we show that information theoretical interpretation of the evolutionary process is useful, in particular in partitioning of network space and measuring of fitness function. The experimental data with 6-input quaternary and 11-inputs binary benchmarks demonstrate the efficiency of our program, EvoDesign, and an improvement against the recently obtained results.

FSM implementation in embedded memory blocks of programmable logic devices using functional decomposition

Since modern programmable devices contain embedded memory blocks, there exists the possibility of implementing finite state machines (FSM) using such blocks. However, the size of the memory available in programmable devices is limited. The paper presents a general method for the synthesis of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible the implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Application of symbolic functional decomposition concept in FSM implementation targeting FPGA devices

This paper presents an FSM implementation method based on symbolic functional decomposition. This novel approach in multilevel logic synthesis of finite state machines targets FPGA architectures. Traditional methods are based on two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementing in FPGA logic cells. The symbolic decomposition does not require separate encoding step. It accepts FSM description with symbolic states and performs decomposition introducing such a state encoding that guarantees the best solution known.