Pradip K. Jha

Fast and accurate resource estimation of RTL-based designs targeting FPGAS

FPGAs have become complex, heterogeneous platforms targeting a multitude of different applications. Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design. For complex designs that involve many iterations and optimizations, the run-time of synthesis can be quite prohibitive. In this paper, we describe a fast and accurate method of estimating the FPGA resources of any RTL-based design. We achieve run-times that are more than 60 times faster than synthesis and is on average within 22% of the actual mapped slices across a large benchmark suite targeting three different FPGA families. This resource estimator tool is first provided in Xilinx PlanAhead 10.1.

Fast RTL Power Estimation for FPGA Designs

This paper presents a fast method of performing RTL power estimation. A context-based, activity propagation engine is used to analyze specific structures identified in the RTL. This estimator was integrated into an FPGA tool flow to provide near instant feedback on expected power dissipation. To fully validate our methodology, a large benchmark suite of designs was used to target three different FPGA families. Our results were compared against a commercial gate-level power estimator. Results show a high level of accuracy (total power average error within 8.1% of a post-route analysis) while achieving a median run-time of 1.84 sec., more than 1000 times faster than a complete place and route flow.