Prakash Harikumar

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

An analog receiver front-end for capacitive body-coupled communication

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in todays system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications

This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications

This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68° while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20°C +85°C].

A 10-bit 50MS/s SAR ADC in 65nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697µW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2. HighlightsThe limitation posed by incomplete DAC settling in medium-to-high speed SAR ADCs is addressed.The design details of a high-speed reference voltage buffer (RVBuffer) are elaborated.Estimation of key performance parameters of the RV Buffer are provided.Post-layout simulation of the full ADC including device noise and IO pad parasitics has been reported.

Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump

This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.

Design of a reference voltage buffer for a 10-bit 1-MS/s SAR ADC

The paper presents the design of a single-ended amplifier in 1.8 V, 180 nm CMOS process for buffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffer such as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation achieves worst-case settling time of 19.3 ns and current consumption of 66 μA while occupying an area of (19.2 μm × 19.2 μm).

An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves -64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuous-time common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68°. Sufficient performance is maintained over process, supply voltage and temperature variations.

Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.