Prakash Periasamy

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

Metal wiring critical dimension shrink using ALD spacer in BEOL sub-50nm pitch

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal critical dimension (CD) shrinkage using atomic layer deposition (ALD) enabled spacer layer to achieve sub-50 nm pitch. ALD spacer thickness is identified as the crucial parameter to achieve target CD. An optimization study correlating oxide thickness, final CD and electrical yield is presented. An optimized recipe that results in 50% shrinkage is identified with good electrical yield.

Cu seed optimization for minimum pitch wiring in 10nm and beyond

Technology scaling necessitates interconnect structures (metal and vias) in the back end of the line (BEOL) module to sub 50nm pitch. This presents significant challenges to the conventional metallization scheme, consisting of liner, seed deposition and Cu plating. Seed layer deposition particularly is quite challenged because of increasing aspect ratio. Additionally, the presence of hard mask in the local metal interconnects (Mx) induces undercut in the metal line profile making metallization even more challenging. The consequence is a significant increase in metal voiding defects as compared to previous technology nodes. Hence the conventional metallization scheme requires reengineering to suit the needs of advanced nodes. In this paper, a systematic approach to tune and optimize the copper seed deposition and its effect on metal electrical yield is presented. Through design of experiments (DOE) the metal open yield (post high temperature anneal-hammer test) improved from less than 10% to greater than 50% for the optimized seed deposition recipe (post stress). The optimized recipe reduced the void related defects responsible for the lower metal open yield. Results from current ramp test, via chain yield and electromigration data will be presented for the optimized seed recipe.

Diagnostic electromigration reliability evaluation with a local sensing structure

EM reliability evaluations generally rely on monitoring an EM test structure resistance increase caused by void formation during current stress. With technology scaling, the height and width of interconnects are shrinking. Therefore, the base resistance of EM test structures increases substantially, and the detection of the absolute resistance change caused by the same size of void at the latest technology nodes becomes very challenging. In this paper, an improved EM test structure based on a local resistance sensing concept is developed and evaluated. With this new test structure and associated method, the location of local void formation can be electrically determined, the details of void evolution can be more fully characterized, and a great improvement of void detection sensitivity can be achieved.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

Electromigration Studies on 6 µm Solid Cu TSV (Via last) in 32 nm SOI Technology

Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration is maturing, reliability is a key parameter to be studied. One such reliability wear-out mechanisms is electro-migration (EM). In this paper, we report on experimental electromigration studies of TSVs used in 3-Dimensional integration (3Di). While TSV themselves can carry large currents, the connection to on-chip wiring -- so called capture levels on both sides of the thinned die are the weakest link from an EM perspective. EM performance of the TSV element itself, the TSV/capture level and TSV/redistribution level (RDL) is investigated using dedicated structures with the respective elements as the weakest link. 300mm 3Di wafers were used using a 32 nm CMOS process with a 6 μm solid Cu TSV integrated at the fat wire levels and our results suggest that this integration scheme exhibits robust EM performance. With the right capture metallizations on both sides of the TSV, we estimate a DC current of 1A per TSV can be sustained for a 10KPOH product. Design methodologies to further improve and better redistribute the current to improve EM performance will be presented.

Optimization of wet clean and its impact on sub-50 nm pitch BEOL yield

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple pattering (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. This scenario has imposed increased demands on many of the semiconductor processes involved in the fabrication of integrated circuits. One such process is the wet clean process. In this paper, a direct correlation between clean chemistry and metal/via electrical yield is shown in M1 module of 10 nm technology node. Line and via open yield improved 10X upon adding iso propyl alcohol (IPA) to the standard dilute hydrofluoric acid (dHF) aqueous solution. IPA acts as an inhibitor, and reduces the surface tension, thus preventing over-aggressive etch and displacement of pattern structures during the clean process.

Point-Contact Metal-Insulator-Metal Architecture: A Facile Approach for Material Screening Studies and Beyond

Historically, the point-contact metal-insulator-metal (MIM) architecture constituted the first approach for making MIM diodes for high-frequency rectification applications. Point-contact MIM rectifiers have been shown to operate at frequencies as high as 150 THz. In the last 3 decades, point-contact architectures have given way to more stable planar MIM architectures that are lithographically patterned to yield micro- and nanoscale device areas. But point-contact MIM architectures are still highly useful, for example, in facilitating high-throughput material screening studies. Such screening studies are of critical importance for developing material design rules to help identify optimal MIM materials for various rectification applications. In this chapter, modified approaches to the point-contact MIM architecture are presented. These architectures are employed to study the influence of material properties on rectification performance. This enables the correlation of performance to the work function values of the two metals, the electron affinity of the insulator and the thermodynamic stability of the metal/insulator interface. Material selection criteria are proposed based on these results. From these criteria a two-dimensional MIM material space map is constructed that can help identify and visualize application-specific champion MIM devices based on their material properties such as work function and electron affinity.