Prasad Venkatraman

Process & design impact on BV DSS stability of a shielded gate trench power MOSFET

This paper discusses the breakdown voltage (BVDSS) characteristics of an n-channel charge balanced shielded gate trench power MOSFET. The study emphasizes on elements that affect the BVDSS stability of such devices to gain good control on design and process/device parameters in order to produce a robust product. Breakdown voltage (BVDSS) walk-in or walk-out can be observed when certain process (e.g., epi doping concentration) and design layout (e.g., termination) conditions are not in coherence.

Modeling and characterization of HDTMOS power technology

The HDTMOS (third generation high density TMOS) technology for low voltage power MOSFETs utilizes a self aligned sidewall spacer to reduce the source contact window. The five layer cell design yields one of the best performing power MOSFETs in the industry for switching applications. 2D process and device simulation of the ISE software package has been used extensively to optimize the device design for the best performance. The actual silicon data is compared to simulation for the validation of modeling work. Further improvements to enhance the performance of HDTMOS3, called HDTMOS3E are discussed.