Zia Hossain

Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process

A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the devices critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the devices critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.

Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance

This paper presents a double-RESURF lateral double-diffused MOS (LDMOS) transistor with a specific on-resistance of lower than 200 m/spl Omega/-cm/sup 2/ while maintaining a breakdown voltage of over 750 V for use in the cost-effective high voltage integrated circuit (HVIC) chip. The proposed double-RESURF high voltage device is monolithically integrated with low voltage analog/logic control circuitry, and is 100% backwards-compatible to ON Semiconductors existing single-RESURF technology. Double-RESURF is a very complicated process to implement, and requires a well-designed device layout with complete charge balance among all the critical layers. This paper will demonstrate a painstaking optimization of key process and device geometrical parameters to maximize the benefits of the double-RESURF phenomenon in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

Determination of Manufacturing Resurf Process Window for a Robust 700V Double Resurf LDMOS Transistor

Resurf (reduced surface field) devices are enormously sensitive to the optimum integrated charge and/or the distribution of charge in the drift region for maintaining a robust breakdown voltage. Nevertheless this optimal charge-balance is often interrupted by the influence of charges in the overlying mold compound and passivation layers, resulting in breakdown voltage degradation under high-voltage, high-temperature stress. As a result, the resurf process window is further squeezed following the reliability stress to maintain the optimal charge balance, hence the target breakdown voltage of over 700 V. This paper presents the optimization of resurf charge for maintaining a robust breakdown voltage, and hence establishes the manufacturing process windows (process implant doses) based on the reliability data in order to minimize yield loss in production.

Process & design impact on BV DSS stability of a shielded gate trench power MOSFET

This paper discusses the breakdown voltage (BVDSS) characteristics of an n-channel charge balanced shielded gate trench power MOSFET. The study emphasizes on elements that affect the BVDSS stability of such devices to gain good control on design and process/device parameters in order to produce a robust product. Breakdown voltage (BVDSS) walk-in or walk-out can be observed when certain process (e.g., epi doping concentration) and design layout (e.g., termination) conditions are not in coherence.

3-D TCAD simulation to optimize the trench termination design for higher and robust BVdss

Optimizing the edge termination design around the periphery of active area is critically important for achieving the highest and stable breakdown voltage (BVDSS) for any power devices. Active cell structures can be assumed as two dimensional (2-D) in the central part of the die, however as the active cells terminate to the termination regions at the periphery of the die, 2-D and 3-D transition regions are formed at different locations of the die layout with respect to the last edge termination trench. Optimization of the 3-D termination region is imperative to ascertain equal or higher BVDSS of the termination region than the active cell region. Synopsys advanced multi-dimensional TCAD device simulation tool - “Sentaurus Device Editor (SDE) [1]” is adopted for designing and optimizing the 3-D termination transition region for a higher and robust BVDSS, which is validated by the experimental data.

Doping engineering for improved immunity against BV softness and BV shift in trench power MOSFET

In this paper, we report typical soft breakdown and BVDSS walk-in/walk-out phenomena observed in the development of ON semiconductors T8 60V trench power MOSFET. These breakdown behaviors show strong correlation with doping profile. We propose two 1D location-dependent variables, Qint(y) and Cave(y), to assist the study, and demonstrate the effectiveness of them in revealing hidden information behind regular SIMS data. Our study details the methodology of engineering doping profiles for improved breakdown stability.

Dielectric RESURF as an alternative to shield RESURF for an improved and easy-to-manufacture low voltage trench MOSFETs

Shielded-gate trench or “Shield RESURF (REduced SURface Field)” MOSFETs have been well known for its lower R<inf>DS(ON) ×</inf>Area, and lower R<inf>ds(on)</inf>×Q<inf>gd</inf> figure of merits (FoMs), and used widely in the low to medium voltage applications (25 V to 200 V). However, this improvement is achieved at the expense of higher output capacitance or output charge (C<inf>oss</inf> or Q<inf>oss</inf>), which has become an increasingly important factor contributing to the MOSFETs switching power loss. In this paper, we will investigate the conventional single gate trench MOSFET structure based on the “dielectric RESURF” principle to offer a simpler wafer processing and consequently cheaper die cost, along with reduced switching losses at the output capacitance (Q<inf>oss</inf>), without compromising much the other key figure of merits such as R<inf>ds(on)</inf>×Area, and R<inf>ds(on)</inf>×Qg.

Modeling and characterization of HDTMOS power technology

The HDTMOS (third generation high density TMOS) technology for low voltage power MOSFETs utilizes a self aligned sidewall spacer to reduce the source contact window. The five layer cell design yields one of the best performing power MOSFETs in the industry for switching applications. 2D process and device simulation of the ISE software package has been used extensively to optimize the device design for the best performance. The actual silicon data is compared to simulation for the validation of modeling work. Further improvements to enhance the performance of HDTMOS3, called HDTMOS3E are discussed.