Pravoslav Martinek

A Contribution to Advanced Extraction Methods for Static ADC Non-linearity

One of the recent approaches for A/D converter performance extraction is the so-called Servo-Loop method. In this paper, we build an improved version of this method targeted to full transistor-level circuit simulation of static integral and differential non-linearity. In comparison with the conventional implementation, the Servo-Loop version proposed was enhanced by a powerful search algorithm. Subsequently, this paper deals with the description of a versatile Servo-Looper tool developed in Verilog-A language suitable for direct co-operation with most of the analog and mixed-signal simulators used in industry. Powerful capabilities of the proposed Servo-Looper tool were successfully confirmed by a large simulation set performed on a full custom ADC design example. The presented paper brings the most significant results of the ADC simulation procedure.

Filter approximation problem using de algorithms

This article introduces a new approach to the filter approximation problem solution. When requirements to the filter cannot be fulfilled by an analytic approximation function, it is necessary to use non-standard methods based on numerical optimization procedures. Here the Differential Evolutionary Algorithm offers far-out solutions. It allows multi-criteria requirements and it is independent on initial condition settings. A newly developed algorithm is described here and the results obtained are demonstrated on some examples.

Developing Automated Design Procedure for Operational Amplifier blocks

This paper deals with the development of automated design procedure (ADP) of analog building blocks dedicated for full-custom integrated circuit design of an operational amplifier (OpAmp). The design procedure proposed is divided into consecutive steps starting from the technology and model card choice followed by the selection of basic blocks for the OpAmp design. Subsequently, the established OpAmp architecture enters an advanced optimization aided by differential evolutionary algorithms. As a result, a robust set of circuit parameters attached to the OpAmp design is obtained, respecting the multi-criterion requirements for analog performance.

A contribution to the 2 nd -order LP filters design

This paper discusses some aspects of design and realization of the simple second-order low-pass building blocks (LP-SFB), suitable for less demanding anti-aliasing and reconstruction filters. The main attention is devoted to the ”single active device” solutions, based on CC-II type current conveyor or transconductance amplifier (OTA). As the template, the Rauchs multiple-feedback circuit was used. Presented SFBs show very low ω0 and Q sensitivities and, in contrast to the known Sallen-Key circuits, save good stop-band attenuation. Proposed design uses DE algorithm and allows almost independent tunning of ω0 and Q parameters.

Versatile sub-bandgap reference IP core

A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35 μm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7 V, low supply voltage from 1.3 V, low power consumption under 10 μA, versatility, high working temperature range from -50 to 95°C. The versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. The IP block is compact, ready to adjust, layout and integrate. The features of the design also allow the in circuit tuning. This example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design.

Versatile engine for virtual testing of ADC/DAC non-linearities

In this paper, we propose a novel versatile engine for behavioral or transistor-level design verification of data converters. This tool is dedicated to IC designers to verify static performance of the converters during their design. It is based on advanced Servo-Loop method presented in [1] and extended by features such as innovative DAC testing method (connecting ADC and DAC testing into one versatile engine). The environment proposed supports various converter resolutions and several types of digital coding. Powerful capabilities of the proposed engine were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.

Experience in Virtual Testing of RSD cyclic A/D converters

This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.

Novel design evaluation engine for A/D converters

Environment for testing analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. Source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). This approach brings to IC design engineers easy to use supportive tool. The core of our proposal is based on Servo- Loop with improved search algorithm [1]. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.

MAPLE program as a Tool for Symbolic Analysis of Digital Filters

The paper introduces a simple tool for symbolic and semisymbolic analysis of digital filters using MAPLE library SYRUP. The library is originally intended for the continuous-time electrical circuit analysis, but, after simple completion can serve for digital circuit analysis as well. Mathematical program MAPLE environment simultaneously enables the post-processing of the results obtained. Some examples showing transfer function H(z) evaluation and the following sensitivity computations, design rules derivation using the modified SYRUP library illustrate the facilities of the presented tool.

Design optimization of wave active filters

This paper deals with design issues related to the realization of wave active filters (WAF). Continuous-time current-mode implementation is considered and the basic building blocks are presented along with their sensitivity properties. A new optimization method of dynamic relations in WAF is derived and its application in practice is explained. Furthermore, the influence of parasitic elements of functional blocks used in WAF on transfer function is discussed. The introduced theory is thereafter utilized by way of a design example.