Prawat Nagvajara

Optimal robust compression of test responses

A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor requires two r-bit registers (r-bit signature) more than a multiple-input linear feedback shift register; however, it provides for equal protection against all error patterns. Therefore, quadratic compressors are optimal and robust with respect to a statistics of errors in a device under test. >

Board-level diagnosis by signature analysis

Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.<<ETX>>

Design of self-diagnostic boards by signature analysis

The authors present a single-faulty-chip diagnostic technique which requires only two reference signatures for any number of chips on the original board. With this technique, it is possible to reduce substantially the hardware overhead compared to the diagnostic technique based on separate testing of each chip on the board. The technique can be also used for identification of faulty printed boards in a system or for identification of faulty processors in a multiprocessor system. >

Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design

This paper presents a custom hardware design for computing Singular Value Decomposition (SVD) of the radio communication channel characteristic matrix. The custom hard-ware was implemented to reduce the SVD computing time. The pipeline hardware developed is suitable for computing the SVD of a sequence of 2 × 2 complex-value matrices used in MIMO-OFDM standards, such as the IEEE 802.11n. The hardware developed achieves an optimum pipeline rate which equaled the maximum hardware clock rate. The proposed architecture provides performance gains over standard software libraries, such as the ZGESVD function of Linear Algebra Package (LAPACK) library, when running on standard processors.

Design, optimization, and implementation of a universal FFT processor

There exist Fast Fourier transform (FFT) algorithms, called dimensionless FFTs, that work independent of dimension. These algorithms can be configured to compute different dimensional DFTs simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows us to design an FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this paper we design a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow, and show how to map different dimensionless FFTs onto this hardware design. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. Using a performance model we search for the optimal algorithm for the family of processors we considered. The resulting algorithm and corresponding hardware design was implemented using FPGA.

Optimal codes for minimax criterion on error detection

Nonlinear quadratic codes that are optimal for the minimax error detection are presented. Characteristic functions for these codes are asymptotically bent. For a given block size n and the number of codewords mod C mod , these codes minimize max Q(e), e not=0, where Q(e) is the conditional error-masking probability, given the error pattern e. The codewords are blocks of n symbols from GF(q). Encoding and decoding procedures for the codes are described. >

Pseudorandom testing for boundary-scan design with built-in self-test

The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-flops in the generator than bits in the test pattern.<<ETX>>

Design-for-Debug: A Vital Aspect in Education

We often assume that debugging is a skill that comes with common sense. However, we have observed that many students do not have an inherent aptitude for debugging. Hands-on projects teaching the engineering design process can become troublesome for some students who cannot complete their projects and consequently fail their courses. In this paper, we advocate the importance of teaching debugging skills throughout digital design courses, especially during the introductory courses. We present teaching techniques in developing the skills for debugging for both introductory and advanced digital design courses. These techniques include emphasis on incremental design stages, test stimuli and observation techniques, and debugging using critical (divergent and convergent) thinking.

Jacobi load flow accelerator using FPGA

Full-AC load flow is a crucial task in power system analysis. Solving full-AC load flow utilizes iterative numerical methods such as Jacobi, Gauss-Seidel or Newton-Raphson. Newton-Raphson is currently the preferred solver used in industrial applications such as power world and PSS/E due to it faster convergence than either Jacobi or Gauss-Seidel. In this paper, we reexamine the Jacobi method for use in a fully pipelined hardware implementation using a field programmable gate array (FPGA) as an alternative to Newton-Raphson. Using benchmark data from representative power systems, we compare the operation counts of Newton-Raphson software to the proposed Jacobi FPGA hardware. Our studies show that Jacobi method implemented in an FPGA for a sufficiently large power system has the potential to be a state of the art full-AC load flow engine.

Real-time seizure detection system using multiple single-neuron recordings

Approximately 20% of people diagnosed with epilepsy cannot be treated effectively. Consequently, there exists a significant need for alternative types of treatment. To aid in the effort of solving this problem, we developed a prototype system to detect changes in neural activity prior to the onset of a seizure. This system can be used as warning device or as part of a large system to terminate seizures in their initial stages via drug administration or nerve stimulation. The detection algorithm used data collected from intracranial electrodes. The waveforms were filtered and amplified to identify single neuron action potentials. The time of occurrence of each action potential for each neuron was then passed to a preprocessor algorithm that summed the data into 50 ms time bins. Sliding windows consisting of 128 bins for each neuron were cross-correlated. The results were summed and the variance of the cross-correlation was used as a measure of global neuron correlation. The algorithm was implemented in a PC board and tested in rats treated with pentylenetetrazol (PTZ) a known seizure inducing drug. The system was 100% effective at detecting seizures approximately 4.6 seconds before seizure onset and had a false positive rate of 0.3%.