Priyanka Saha

Performance analysis of a high speed, energy efficient 4×4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET

The objective of this paper is fully focused on designing of a power efficient, high performance 4×4 1T DRAM cell array using conventional MOS, fully depleted SOI/SON and CNFET devices. As the CMOS technology is being scaled down, there has been a major need to improve the performance and robustness of the memory extensively used in todays hand-held devices. Dynamic Random Access Memory (DRAM) is the main memory used for all desktop and larger computers. In modern VLSI circuit designing, power dissipation is also a crucial issue. The new emerging devices with improved technology promise of low power applications. In this paper, we have presented a comparative circuit level analysis between Metal Oxide Semiconductor (MOS), fully depleted Silicon on Insulator (FD-SOI), fully depleted Silicon on Nothing (FD-SON) and Carbon Nanotube Field Effect transistor (CNFET) in 32nm technology node using HSpice tool.

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

On the Dynamics of a Discrete Predator–Prey Model

We here discretize a predator–prey model by standard Euler forward method and non-standard finite difference method and then compare their dynamic properties with the corresponding continuous-time model. We show that NSFD model preserves positivity of solutions and is completely consistent with the dynamics of the corresponding continuous-time model. On the other hand, the discrete model formulated by forward Euler method does not show dynamic consistency with its continuous counterpart. Rather it shows scheme-dependent instability when step-size restriction is violated.

Analytical Modeling and Simulation of Triple Metal Front Gate Stack DG-MOSFET with Graded Channel (GC-TMDG MOSFET)

This paper presents an explicit 2D analytical surface potential modeling of Triple Metal Front Gate Stack DG MOSFET with Graded Channel (GC-TMDG MOSFET) to explore the dual benefits of gate and channel engineering techniques. The surface potential profile of the proposed model is derived by solving 2D Poisson’s equation with suitable boundary conditions and also compared with graded channel DG MOSFET and Triple Material DG MOSFET to establish the superiority of our structure. In addition to this, lateral electric field closer to drain end is examined to substantiate the immunity of the device to hot carrier effect. For validation of analytical model, all the results are compared with 2D ATLAS device simulator data.

Hierarchical Metadata-Based Secure Data Retrieval Technique for Healthcare Application

The metadata representation in the context of data privacy is one of the biggest challenges in data security. The segregation of the data attributes for secure data retrieval as well as data storage is the primary motivation for this work. The metadata-based data retrieval is performed for providing a layer of protection on the actual data set and also for efficiently searching the location of encrypted data. The paper aims to provide a technique for representing the metadata of the encrypted e-health data for a secure data retrieval process. The hierarchical representation of metadata helps in retrieving the data in an efficient way so that access to the sensitive information could be controlled. The paper proposes a novel technique for metadata design for secure data retrieval. E-health data is fragmented over multiple servers based on sensitive attribute and sensitive association. A brief overview of the data protection and data retrieval techniques with respect to the proposed metadata representation is also presented.

Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

AbstractThis paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson’s equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.

3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor

ABSTRACT This work presents a detailed three-dimensional analytical modelling and simulation study of a dual material tri-gate (DM TG) tunnelling field effect transistor (TFET) obtained by intermixing the concepts of tri-gate architecture and dual material gate in the widely popular TFET structure. The proposed model aims to tune the tunnelling barrier in the channel region at the source channel junction so that the band-to-band tunnelling of carriers occurs at a significant rate and reaches the drain region efficiently under the influence of enhanced gate control over the channel region, thereby increasing the device ON current. An overall performance comparison of the proposed DM TG-TFET with that of its single-metal tri-gate (SM TG) TFET counterpart has been depicted to establish the effectiveness of the proposed DM TG-TFET structure. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

Threshold Voltage Modelling of Linearly Graded Binary Metal Alloy Gate Electrode with DP MOSFET

Abstract Two-dimensional (2D) analytical threshold voltage model for Linearly Graded Binary Metal Alloy (LGBMA) gate electrode with Dielectric Pocket (DP) Metal Oxide Semiconductor (MOSFET) has been developed by solving 2-D Poisson’s equation using evanescent mode analysis technique. In this proposed model, first time the idea of work function engineering is incorporated for DP MOSFET to bring an improvement over different short channel effects (SCEs). In present paper, the expressions for surface potential and threshold voltage are derived along with drain current, transconductance and drain conductance. Moreover, this model also predicts the variations of different SCEs like threshold voltage roll off, Drain-induced Barrier Lowering (DIBL) and sub-threshold swing along the channel length correctly. All analytical results are verified by ATLAS-2D simulator.

Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor

This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the devices immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poissons equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

Analytical Modelling and Performance Analysis of Dielectric Pocket-Induced Double-Gate Tunnel Field-Effect Transistor

ABSTRACT In this paper, a dielectric pocket-induced double-gate tunnel field-effect transistor is presented for improving the ON state current and suppressing the ambipolar conduction of the device. Introduction of dielectric pocket at the junction of both source and drain helps to tune the tunnelling barrier and subsequently controls the tunnelling current. A physics-based analytical model of surface potential and electric field is deduced by solving 2D Poissons equation.Tunnelling current is then derived using Kanes model. The performance of this structure is then studied by varying the dielectric material of the pocket at source/drain junctions. Analytical results have been compared with the SILVACO ATLAS simulated results for verification of our model.