Saheli Sarkhel

Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

An overall performance comparison analysis based on 2-D Poissons equation solution has been presented here both for silicon-on-insulator (SOI) and silicon-on-nothing (SON) MOSFET structures. In this paper, for the first time, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented analytically to reduce rolloff in threshold voltage for SON MOSFET, thereby improving its performance over single-gate SON structures. Analytical model-based simulation verified that SON is superior over SOI MOSFET due to its higher immunity to different short-channel effects and increased current driving capability. Our results are found to be in good agreement with simulation results, thereby verifying the accuracy of the proposed analytical model.

Recent research trends in gate engineered tunnel FET for improved current behavior by subduing the ambipolar effects: A review

The gradual progress in the development of a Tunnel Field Effect transistor as a suitable alternative to conventional Metal Oxide Semiconductor Field Effect Transistor for achieving superior current performance in nanoscale low power device has been considered in this review. Beginning from a simple p-i-n reverse biased diode, we have tried to cover various recently developed gate engineered TFET structures in terms of their current behavior to show that by cleverly engineering the gate electrode, TFETs with superior current characteristics can be realized. Apart from this, we have also presented a concise discussion on the problem and possible solution of ambipolarity in TFETs, thereby making the use TFETs with low leakage current possible in complimentary digital circuits.

Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance

ABSTRACT The present boon in the research field of nanoscale device physics is attributed to a large extent by the development of non-conventional multiple gate MOS devices due to increased device packing density and enhanced gate electrostatic control over the channel. In this work, we have investigated the attributes of an asymmetric Double Gate metal oxide semiconductor field effect transistor (MOSFET) incorporating the novel theory of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate in a fully depleted Double Gate MOSFET. A two-dimensional analytical modeling of this Linearly Graded Asymmetric Double Gate MOSFET structure has been done to formulate a simplified expression for short channel threshold voltage, and an overall performance analysis of our proposed device has been presented to establish the superiority of our proposed structure in terms of superior short channel effect mitigation and a significant reduction in threshold voltage. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby, establishing the accuracy of our model.

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

Analytical Modeling and Simulation of Triple Metal Front Gate Stack DG-MOSFET with Graded Channel (GC-TMDG MOSFET)

This paper presents an explicit 2D analytical surface potential modeling of Triple Metal Front Gate Stack DG MOSFET with Graded Channel (GC-TMDG MOSFET) to explore the dual benefits of gate and channel engineering techniques. The surface potential profile of the proposed model is derived by solving 2D Poisson’s equation with suitable boundary conditions and also compared with graded channel DG MOSFET and Triple Material DG MOSFET to establish the superiority of our structure. In addition to this, lateral electric field closer to drain end is examined to substantiate the immunity of the device to hot carrier effect. For validation of analytical model, all the results are compared with 2D ATLAS device simulator data.

3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor

ABSTRACT This work presents a detailed three-dimensional analytical modelling and simulation study of a dual material tri-gate (DM TG) tunnelling field effect transistor (TFET) obtained by intermixing the concepts of tri-gate architecture and dual material gate in the widely popular TFET structure. The proposed model aims to tune the tunnelling barrier in the channel region at the source channel junction so that the band-to-band tunnelling of carriers occurs at a significant rate and reaches the drain region efficiently under the influence of enhanced gate control over the channel region, thereby increasing the device ON current. An overall performance comparison of the proposed DM TG-TFET with that of its single-metal tri-gate (SM TG) TFET counterpart has been depicted to establish the effectiveness of the proposed DM TG-TFET structure. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

Analytical Modeling and Performance Characterization of a Double Gate MOSFET with Dielectric Pockets Incorporating Work Function Engineered Binary Metal Alloy Gate Electrode for Subdued SCEs

ABSTRACT In this work, double gate MOSFET with dielectric pocket has been proposed by incorporating the concept of gate work function engineering. A comparative analysis of this proposed structure with a normal double gate dielectric pocket MOSFET without gate work function engineering has been investigated in terms of surface potential, channel electric field distribution, and threshold voltage in order to establish the superiority of the proposed structure in subduing short channel effects. The analytical results are in good agreement with simulated results, thereby validating the accuracy of the analytical model.

Parasitic fringe capacitance modeling of work function engineered double gate TFET

In the recent trend of device dimension scaling, parasitic capacitances play pivotal role in determining device performance in ultra low power high speed circuits. In view of this, we have attempted to present a brief study on the analytical modeling of parasitic fringe capacitance of a Tunneling Field Effect transistor with linearly graded binary metal alloy double gate electrode and investigate the impact of device parameters on the capacitance values with an aim to optimize the device parameters in order to bring an improvement in overall device delay performance for future high speed circuits. The obtained analytical results have been compared with SILVACO ATLAS device simulator results for verification of our proposed model.

Analytical model for I D -V D characteristics of a triple metal double gate TFET

In the present era of nano dimensional devices, several non-conventional device structures are being proposed by researchers to satisfy the trend of continuous device dimension down-scaling. As one such non-conventional structure, the Tunneling Field Effect Transistors (TFETs) are now being investigated with tremendous attention due to the inherent advantage of carrier conduction by band-to-band tunneling mechanism which in turn mitigates various Short Channel Effects (SCEs). This work presents a two dimensional analytical model for the drain current evaluation of a triple metal double gate TFET. The work functions of the three metals used in the gate electrode are chosen in such a way that the reverse tunneling of carriers from drain to source can be mitigated. The variation of drain current for different device parameters has been studied and also verified with SILVACO TCAD simulator.

Small - signal parameter extraction to study the RF performance of SOI and SON MOSFET

A simple small-signal equivalent circuit for generalized horizontal SOI and SON MOSFET has been presented. The intrinsic parameters of the small-signal model are obtained from a compact capacitance based analytical model Using those small-signal model parameters, frequency dependent performances of those structures are simulated with SILVACO SMART SPICE RF Module. It has been realized that SON technology improves the frequency response due to improved conductance and reduced parasitic effects. This type of combined analytical and simulation approach allows us to predict the technology road map for future ultra dense, low power nanoelectronics devices and their efficiency in RF frequency range.