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Dive into the research topics where Puo-Yu Chiang is active.

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Featured researches published by Puo-Yu Chiang.


international reliability physics symposium | 2011

Investigation of multistage linear region drain current degradation and gate-oxide breakdown under hot-carrier stress in BCD HV PMOS

Y.-C. Huang; J.R. Shih; C.C. Liu; Y.-H. Lee; R. Ranjan; Puo-Yu Chiang; Dah-Chuen Ho; Kenneth Wu

Hot-carrier injection (HCI) at maximum gate current (IG) stress condition for BCD HVPMOS has been studied. It is found that HCI not only causes linear region drain current degradation and minimizes the operation window, but also degrades the gate oxide (GOX) and may result in GOX breakdown. A multistage IDlin degradation behavior has been observed during HCI stress, which is associated with two competing mechanisms, i.e., interface-state (Nit) generation and electron trapping caused by hot electrons originated from impact ionization. HCI leads to the gate oxide breakdown even at very low e-field of ∼1.5MV/cm across the GOX. TCAD simulation results by placing Nit and negative charges at different location of the device also support a multistage IDlin degradation. It is found that both initial IG and bulk current (IB) are well correlated with GOX time-dependent-dielectric-breakdown (TDDB). In addition, better TDDB has been observed at higher temperature compared to lower temperature, which verifies that GOX breakdown is associated with HCI.


Archive | 2008

Lateral power MOSFET with high breakdown voltage and low on-resistance

Tsung-Yi Huang; Puo-Yu Chiang; Ruey-Hsin Liu; Shun-Liang Hsu


Archive | 2007

HIGH VOLTAGE DEVICE WITH LOW ON-RESISTANCE

Puo-Yu Chiang; Tsung-Yi Huang; Fu-Hsin Chen; Ting-Pang Li; Chung-Yeh Wu


Archive | 2010

HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES

Chih-Wen Yao; Robert S. J. Pan; Ruey-Hsin Liu; Hsueh-Liang Chou; Puo-Yu Chiang; Chi-Chih Chen; Hsiao Chin Tuan


Archive | 2010

Gate Electrodes of HVMOS Devices Having Non-Uniform Doping Concentrations

Ru-yi Su; Puo-Yu Chiang; Jeng Gong; Tsung-Yi Huang; Chun-Lin Tsai; Chien-chih Chou


Archive | 2008

Stabilizing Breakdown Voltages by Forming Tunnels for Ultra-High Voltage Devices

Eric Huang; Tsung-Yi Huang; Fu-Hsin Chen; Chyi-Chyuan Huang; Puo-Yu Chiang


Archive | 2008

Disconnected DPW Structures for Improving On-State Performance of MOS Devices

Chih-Wen Yao; Puo-Yu Chiang; Tsai Chun Lin; Tsung-Yi Huang


Archive | 2008

Schottky Diode Structures Having Deep Wells for Improving Breakdown Voltages

Puo-Yu Chiang; Tsai Chun Lin; Chih-Wen Albert Yao; David Ho


Archive | 2010

Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device

Ruey-Hsin Liu; Puo-Yu Chiang; Chih-Wen Yao; Yu-Chang Jong; Hsiao-Chin Tuan


Archive | 2011

Integrated circuit apparatus and manufacturing method thereof

Ruey-Hsin Liu; Puo-Yu Chiang; Chih-Wen Yao; Yu-Chang Jong; Hsiao-Chin Tuan

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