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Dive into the research topics where Chih-Wen Yao is active.

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Featured researches published by Chih-Wen Yao.


international symposium on power semiconductor devices and ic's | 2012

0.18 µm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs

Hsueh-Liang Chou; P. C. Su; J. C. W. Ng; P. L. Wang; H. T. Lu; C. J. Lee; W. J. Syue; S. Y. Yang; Y. C. Tseng; Chih-Chang Cheng; Chih-Wen Yao; R. S. Liou; Y. C. Jong; J. L. Tsai; Jun Cai; H. C. Tuan; Chih-Fang Huang; Jeng Gong

This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm2 for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the ID-VD saturation region of most of the high voltage LDMOS devices is significantly suppressed.


Archive | 2013

High voltage resistor

Chih-Chang Cheng; Ruey-Hsin Liu; Chih-Wen Yao; Ru-Yi Su; Fu-Chih Yang; Chun Lin Tsai


Archive | 2010

HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES

Chih-Chang Cheng; Ruey-Hsin Liu; Chih-Wen Yao; Chia-Chin Shen; Eric Huang; Fu Chin Yang; Chun Lin Tsai; Hsiao-Chin Tuan


Archive | 2010

HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES

Chih-Wen Yao; Robert S. J. Pan; Ruey-Hsin Liu; Hsueh-Liang Chou; Puo-Yu Chiang; Chi-Chih Chen; Hsiao Chin Tuan


Archive | 2010

Semiconductor Device Having Multi-Thickness Gate Dielectric

Hsueh-Liang Chou; Ruey-Hsin Liu; Chih-Wen Yao; Hsiao-Chin Tuan


Archive | 2013

QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE

Chih-Chang Cheng; Ruey-Hsin Liu; Chih-Wen Yao; Hsiao Chin Tuan


Archive | 2008

Disconnected DPW Structures for Improving On-State Performance of MOS Devices

Chih-Wen Yao; Puo-Yu Chiang; Tsai Chun Lin; Tsung-Yi Huang


Archive | 2010

Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device

Ruey-Hsin Liu; Puo-Yu Chiang; Chih-Wen Yao; Yu-Chang Jong; Hsiao-Chin Tuan


Archive | 2011

LOCALIZED CARRIER LIFETIME REDUCTION

Alex Kalnitsky; Chih-Wen Yao; Jun Cai; Ruey-Hsin Liu; H. C. Tuan


Archive | 2017

POWER MOSFETS AND METHODS FOR MANUFACTURING THE SAME

Yogendra Yadav; Chi-Chih Chen; Ruey-Hsin Liu; Chih-Wen Yao

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