Pushpa Mahalingam

Challenges of High-Precision Capacitor Integration

A robust, reliable method of building high-precision MIM (metal-insulator-metal) capacitors with low Vcc, high matching performance and integrated in a 0.18um mixed signal process with sub- 0.35um metallization rules has been demonstrated. Top plate and hardmask materials, along with the influence of top plate etch on defect density have been presented. An innovative method of reducing voltage coefficient for a MIM capacitor has also been reported.

Manufacturing challenges and method of fabrication of on-chip capacitive digital isolators

A robust and innovative method of fabrication of on-chip capacitive digital isolators integrated in a high precision analog CMOS process is presented in this paper. Several dielectric materials such as TEOS, HDP, silicon nitride, silicon oxynitride, with different film stresses were evaluated for this capacitor in order to achieve the high breakdown voltage (RMS and surge) requirements of the isolation capacitor while ensuring wafer manufacturability. Impact of various integration schemes and combinations of the dielectric layers on the capacitor breakdown voltage performance along with a package and wafer-level reliability assessment of these integration schemes is discussed.

Influence of starting material on analog technology fabrication yield and device component performance

Choice of substrate used for analog complementary metal-oxide-semiconductor (CMOS) technologies impacts device performance and fabrication yields significantly. This study examines the impact of low-angle (<5°) off-axis Si(100) substrate rotated around ⟨110⟩ axis and 0° Si(100) on-axis starting material on inline process control, parametric device performance, and ultimately fabrication yields. The interaction of thermal processes and silicon epitaxial growth process variation on inline photoalignment and its influence on device design and performance is discussed for both types of substrates. The device components include 3 and 5V analog CMOS, lateral p-n-p bipolar transistor, junction field effect transistors, and drain extended transistors, DENMOS and DEPMOS, where the drain extensions are formed using well implants. The necessity to reintegrate silicon epitaxial growth, well photolithography and implants, Vt implants, and gate oxide process loop to accommodate substrate crystal orientation changes wil...

Thin-Gate CMOS and Super-Thick Gate DECMOS Integration in 0° On-axis ≪100≫ Starting Wafer: Process Challenges and Solutions

In this paper, we report detailed studies on process challenges and solutions when super-thick gate DECMOS and thin gate CMOS are integrated together in 0deg on-axis <100> substrate. It has been found that large intra-wafer VT variation (sigma ~ 90 mV) and inter-wafer VT offset (~150 mV) are caused by single (f high energy WELL implant and front and back wafer surface swapping. A high energy implant method has been found very effective in reducing the VT variation to a ~30 mV. Low gate oxide breakdown at the thin gate active region edge has been solved by adding super-thick gate oxide buffer region between thin gate oxide and field oxide. Proper integration sequence has been used to minimize dopant ashout.

Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.