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Dive into the research topics where Sopa Chevacharoenkul is active.

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Featured researches published by Sopa Chevacharoenkul.


IEEE Transactions on Magnetics | 2017

Fabrication and Performance of Integrated Fluxgate for Current Sensing Applications

Dok Won Lee; Mona M. Eissa; Ann Gabrys; Byron J. R. Shulver; Erika Mazotti; Sudtida Lavangkul; Sopa Chevacharoenkul; Neal T. Murphy; Fuchao Wang; Yousong Zhang; Will French; Mark L. Jenson; Ricky A. Jackson

The recently developed Fluxgate technology from Texas Instruments has enabled the production of the industry’s first current sensing integrated circuit with a fully integrated fluxgate device and a compensation coil driver. This paper presents an overview of the Fluxgate technology, focusing on the fabrication and performance of the integrated magnetic field sensing device.


Proceedings of SPIE, the International Society for Optical Engineering | 2006

Across wafer focus mapping and its applications in advanced technology nodes

Gary Zhang; Stephen J. DeMoor; Scott William Jessen; Qizhi He; Winston Yan; Sopa Chevacharoenkul; Venugopal Vellanki; Patrick Reynolds; Joe Ganeshan; Jan Hauschild; Marco Pieters

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact the device yield. A technique based on the Phase-Shift Focus Monitor (PSFM) is developed to measure realistic across-wafer focus errors on materials processed in actual production flows. With this technique, we are able to extract detailed across-wafer focus performance at critical pattern levels from the front end of line (FEOL) all the way through the back end of line (BEOL). Typically, more than 8,000 data points are measured across a wafer, and the data are decomposed into an intra-field focus map, which captures the across chip focus variation (ACFV), and an inter-field focus map, which describes the across wafer focus variation (AWFV). ACFV and AWFV are then analyzed to understand various components in the overall focus error, including; across slit lens image field, reticle shape and dynamic scan components, local wafer flatness, wafer processing effect, pattern density, and edge die abnormality. The intra-field ACFV lens component is compared with TIs ScatterLith and ASMLs FOCAL techniques. Results are consistent with the predictions based on the on-board lens aberration data. Inter-field AWFV is the most interesting, due to lack of detailed understanding of the process impact on scanner focus and leveling. PSFM data is used to characterize the effect of wafer processing such as etch, deposition, and CMP on across wafer focus control. Comparison and correlation of PSFM focus mapping with the wafer height and residual moving average (MA) maps generated by the scanners optical leveling sensors shows a good match in general. Process induced focus errors are clearly observed on wafers of significant film stack variation and/or pattern density variation. Implications on total focus control and depth of focus (DOF) requirements for 65nm mass production are discussed in this paper using a quantitative pattern yield model. The same technique can be extended to immersion lithography.


Archive | 2010

Single step CMP for polishing three or more layer film stacks

Eugene C. Davis; Binghua Hu; Sopa Chevacharoenkul; Prakash D. Dev


Archive | 2009

Selective plasma etch of top electrodes for metal-insulator-metal (mim) capacitors

Marshall O. Cathey; Pushpa Mahalingam; Weidong Tian; David Guiling; Xinfen Chen; Binghua Hu; Sopa Chevacharoenkul


Archive | 2006

SEMICONDUCTOR DEVICE MANUFACTURED BY REDUCING HILLOCK FORMATION IN METAL INTERCONNECTS

Ju-Ai Ruan; Changming Jin; Sopa Chevacharoenkul; Satyavolu Srinivas Papa Rao; Tae Seung Kim


Archive | 2008

Method to prevent localized electrical open cu leads in vlsi cu interconnects

Sopa Chevacharoenkul; Phillip D. Matz


Archive | 2009

Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes

Marshall O. Cathey; Pushpa Mahalingam; Weidong Tian; David Guiling; Xinfen Chen; Binghua Hu; Sopa Chevacharoenkul


Archive | 2018

INTEGRATED TRENCH CAPACITOR WITH TOP PLATE HAVING REDUCED VOIDS

Binghua Hu; Abbas Ali; Sopa Chevacharoenkul; Jarvis B. Jacobs


Archive | 2017

SELECTIVE PATTERNING OF TITANIUM ENCAPSULATION LAYERS

Lee Alan Stringer; Mona M. Eissa; Byron J. R. Shulver; Sopa Chevacharoenkul; Mark R. Kimmich; Sudtida Lavangkul; Mark L. Jenson


Archive | 2017

LAYOUTS FOR INTERLEVEL CRACK PREVENTION IN FLUXGATE TECHNOLOGY MANUFACTURING

Sudtida Lavangkul; Sopa Chevacharoenkul

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