Pushpa Rajaguru

Electro-thermo-mechanical modelling and analysis of the press pack diode in power electronics

This paper details a finite element modelling approach of the press pack assembly process for a diode in a power electronic module. Molybdenum and aluminum graphite have been investigated as suitable materials for the contact pad. Contact analysis has been used to model the pressurized thermal interface in order to extract both the stress and temperature distribution in the diode. Average temperature and von Mises stress on the chip for a combination of clamping pressure, load current and contact pad material have been extracted from the modeling results. At present, based on the assumptions and modeling parameters used, Aluminum Graphite seems to have better performance in comparison with molybdenum in terms of generating a lower average chip temperature. Additionally optimum clamping pressure has been estimated by performing a numerical optimisation analysis in order to minimise both the average temperature and stress in the chip.

Reduced order modelling for risk mitigation in design of miniaturised/integrated products

A numerical modelling methodology for the embodiment design of three-dimensional miniaturised/integrated products is developed and demonstrated. The focus is on the numerical techniques and methods that underpin the development of reduced order models (ROMs). These models are used together with methods for estimating variations in performance/quality characteristics and probabilistic optimisation to aid sensitivity, product capability and risk mitigation analyses. The numerical techniques comprising the design methodology are demonstrated with examples related to the design of a novel three-dimensional vibrating micro-probe.

Numerical modelling methodology for design of miniaturised integrated products - an application to 3D CMM micro-probe development

This paper presents an integrated numerically-driven modelling methodology for the design of miniaturised/integrated (Mintegrated) products and the selection/control of associated manufacturing processes. The focus is on the numerical techniques and methods that underpin several design procedures aiding the embodiment design stage of product development. A design assistant tool is developed as an end-user navigation interface that captures recommended design activities for the development of novel micro-integrated products and the supporting tools for their realisation. The main focus is placed on those design procedures comprising numerical methods for the simulation and modelling of the performance and behaviour of a product or process, and the analysis of their design in terms of risk of failure, capability of satisfying specification limits and optimality. The methodology enables an efficient and fast design process and can be applied to a wide range of micro-product developments. The applications range from the fabrication of micro- and nano-scale structures and components for heterogeneous systems, to micro-fluidics, metrology and embedded test devices. In this study, a number of design procedures and associated numerical techniques are demonstrated for the design of a new three-dimensional coordinate measuring machine (CMM) micro-probe developed at the National Physical Laboratory (NPL, UK).

Evaluation of the impact of the physical dimensions and material of the semiconductor chip on the reliability of Sn3.5Ag solder interconnect in power electronic module: A finite element analysis perspective

This paper primarily focuses on an evaluation study for the temperature cycling capability of tin silver solder interconnect in power electronic applications by the impact of die dimensions and die material properties. The study was investigated on finite element analysis perspective on chip/solder/substrate structure. A commercially available chip was chosen in the finite element analysis (FEA) as the nominal base die. Two thermal cycle profiles were utilised. The effect of die area, die thickness and material properties (Si and SiC) on the thermal cycling capability of the solder layer was investigated from FEA perspective. From the FEA, it was concluded that decrease in die thickness resulting in increment of thermal cycling capability of solder layer for both material (Si and SiC). Increase in die area increases the thermal cycling capability of solder. For higher ΔT thermal cycle, solder under SiC die perform better than solder under Si die in terms of thermal cycling capability. When the die thickness become smaller than a threshold value of the thermal cycle regime, solder under Si die have better thermal cycling capability than solder under SiC die. Additionally a parametric study was undertaken for a SiC chip/substrate structure under high ∆ T temperature cycling profile for solder layer geometric parameter (wetting angle, titling angle and thickness). From the parametric study which utilised design of experiments (DoE), a wavelet radial basis surrogate model was generated. A sensitivity analysis was performed on surrogate model in order to identify the most influencing parameter. From the sensitivity analysis, it was concluded that wetting angle and solder layer thickness of solder layer have significant impact on the thermal cycling capability of the solder layer.