Q. Ouyang

Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability

Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.

Vertical P-MOSFETs with heterojunction between source/drain and channel

The growth of high quality strained SiGe-Si and SiGeC-Si heterostructures allows incorporation of band gap engineering into Si technology, which can be used to improve device characteristics. A heterojunction MOSFET (HJMOSFET) structure has been proposed in which the large valence band offset at SiGe-Si heterojunctions reduces the punchthrough and DIBL for P-MOSFETs (Hareland et al, 1993). Vertical MOSFETs allow more freedom in terms of band gap engineering, and the channel length is not limited by the lithography (Liu et al, 1998). In this paper, we show experimentally that the heterojunction at the source can be used to suppress the floating body effect and short channel effect. Vertical P-MOSFETs with strained SiGe and SiGeC sources have been fabricated with 60-75 nm effective channel lengths. The electrical characteristics of the devices are compared with those of control Si devices and with simulation results.

Models for electron and hole mobilities in MOS accumulation layers

We present new physically based effective mobility models for both electrons and holes in MOS accumulation layers. These models take into account carrier-carrier scattering, in addition to surface roughness scattering, phonon and fixed interface charge scattering, and screened Coulomb scattering. The newly developed effective mobility models show excellent agreement with experimental data over the range 1/spl times/10/sup 16/-4/spl times/10/sup 17/ cm/sup -3/ for which experimental data are available. Local-field dependent mobility models have also been developed for both electrons and holes, and they have been implemented in the two-dimensional (2-D) device simulators, PISCES and MINIMOS, thus providing for more accurate prediction of the terminal characteristics in deep submicron CMOS devices. In addition, transition region mobility models have been developed to account for the transition in the mobility in going from the accumulation layer in the gate-to-source overlap region to the inversion layer region in the channel.

Bandgap engineering in deep submicron vertical pMOSFETs

Bandgap engineering in SiGe heterojunction bipolar transistors (HBT) and high-mobility SiGe channel pMOSFETs significantly enhances the device performance. This study, for the first time, further explores the application of Si-SiGe heterostructures in tailoring MOSFET channel potentials for improving the performance of deep submicron pMOSFETs, and provides guidance for experimental work.

Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs

High permittivity (K) gate insulators are projected for sub-100 nm Si MOSFETs since direct tunneling will likely limit SiO/sub 2/ thicknesses to 1.0-1.5 nm. High-K insulators avoid tunneling, but their larger physical thicknesses introduce subtle capacitive coupling phenomena such as fringing-induced barrier lowering (FIBL) that can compromise off-state leakage. In this study, device simulation examines both on and off-state drain current with very high-K gate insulators and sidewall spacers to reveal new source-side and boundary condition effects. Asymmetric devices help to distinguish the effects. A study of stacked gate insulators demonstrates a 10% increase in drive current achieved with high-K spacers in 50 nm devices.

The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory

A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The simulation method incorporates both electron and hole Monte Carlo analysis to calculate this secondary electron gate current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues to increase for smaller channel length (50/spl times/ from L/sub g/-03.39 to 0.12 /spl mu/m) and higher substrate doping (more than 6/spl times/ when doubled) in scaled, low-power flash memory.

An asymmetric Si/Si1−xGex channel vertical p-type metal-oxide-semiconductor field-effect transistor

Abstract In this study, we discuss a vertical p-type metal-oxide-semiconductor field-effect transistor device structure with an asymmetric Si/Si1−xGex deep submicron (100 nm) channel. The source and source end of the channel are made of Si while rest of the channel and the drain are made of strained Si1−xGex. Compared with conventional Si device, the drive current of this asymmetric channel device is improved due to high electric field near the source end, high pinchoff voltage and high hole mobility in the strained Si1−xGex layer. The short channel effects and punchthrough are not degraded because the source and channel junction is made of Si, instead of strained Si1−xGex which has a smaller band gap.

Modeling of direct tunneling current through gate dielectric stacks

The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schrodingers equation and allowing for wave function penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The WKB solution agrees well with the tunneling currents predicted by this technique. For the same effective oxide thickness (EOT), the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-k dielectrics as gate insulators, the interfacial oxide must be eliminated. We also present for the first time the C-V curves obtained assuming that the wave function penetrates into the oxide.

SiGe heterojunction vertical p-type metal–oxide–semiconductor field-effect transistors with Si cap

SiGe source heterojunction p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) have been used before to suppress the short channel effect for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the heterojunction. In this letter, we discuss a SiGe source heterojunction vertical p-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering (DIBL) effect and floating body effect are still suppressed. The electrical characterization of the device shows it exhibits higher drive current and less DIBL compared with a Si control device.

Si/sub 1-x/Ge x channel vertical PMOSFET with asymmetric Ge profile

Describes a vertical PMOSFET with an asymmetric Si/Si/sub 1-x/Ge/sub x/ channel . On the source side, the channel is made of Si, so the short channel performance is not degraded compared with a Si device. The rest of the channel is made of strained Si/sub 1-x/Ge/sub x/. and we still can take advantage of the high hole mobility in the strained Si/sub 1-x/Ge/sub x/ layer. The energy step in the channel increases the lateral electric field near the source and helps with carrier injection from the source to the channel. Ultra-high vacuum chemical vapor deposition (UHV-CVD) was used to grow the device layers with in situ doping.