Yi Yangbo

The Influence on the Performance of Power Double Diffused MOSFET with Different Gate Layout Geometries

Abstract The influence on the performance of power Double Diffused MOSFET (DMOS) with different gate layout geometries has been analyzed. The investigation shows that the gate layout geometry will greatly affect the dopant concentration of the channel region, so as to influence the average threshold voltage shift and the breakdown voltage. The internal mechanism has also been explained and analyzed in detail, so as to find out the optimization design of the polygate geometry.

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

Thermal characteristics investigation of high voltage grounded gate-LDMOS under ESD stress conditions

The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators. The total heat and lattice temperature distributions along the Si-SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail. The influence of structure parameters on peak lattice temperature is also discussed, which is useful for designers to optimize the parameters of LDMSO for better ESD performance.