Qinghong Bu

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65 nm CMOS front-end consumes 319 mW and 223 mW in transmitting and receiving mode, respectively, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards. The 40 nm CMOS baseband incorporating LDPC consumes 196 mW and 398 mW for 16QAM in transmitting and receiving mode, respectively. The entire system, using a 6dBi antenna built in an organic package, can transmit 3.1Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A 24 dB gain 51–68 GHz CMOS low noise amplifier using asymmetric-layout transistors

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). A 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. By using the asymmetric-layout transistor, a four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS

This paper presents a 16QAM direct-conversion transceiver in 65nm CMOS, which is capable of 60-GHz wireless standards. The capacitive cross-coupling neutralization contributes a high common-mode rejection and a high reverse isolation, and a fully-balanced mixer can improve the error vector magnitude due to the reduced local leakage. The maximum data rates with an antenna built in a package are 10Gb/s in QPSK mode and 16Gb/s in 16QAM mode and the transmitter and the receiver consume 181mW and 138 mW, respectively.

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Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

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A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS

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High-Q inductors on locally semi-insulated Si substrate by helium-3 bombardment for RF CMOS integrated circuits

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A 0.015-mm 2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs

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