Qingsong Shi

Less reused filter: improving l2 cache performance via filtering less reused lines

The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines that are never reused or reused for few times. In this case, the cache performance can be improved through retaining a portion of working set in cache for a period long enough. Previous schemes approach this by bypassing never reused lines. Nevertheless, severely constrained by the number of never reused lines, sometimes they deliver no benefit due to the lack of never reused lines. This paper proposes a new filtering mechanism that filters out the less reused lines rather than just never reused lines. The extended scope of bypassing provides more opportunities to fit the working set into cache. This paper also proposes a Less Reused Filter (LRF), a separate structure that precedes L2 cache, to implement the above mechanism. LRF employs a reuse frequency predictor to accurately identify the less reused lines from incoming lines. Meanwhile, based on our observation that most less reused lines have a short life span, LRF places the filtered lines into a small filter buffer to fully utilize them, avoiding extra misses. Our evaluation, for 24 SPEC 2000 benchmarks, shows that augmenting a 512KB LRU-managed L2 cache with a LRF having 32KB filter buffer reduces the average MPKI by 27.5%, narrowing the gap between LRU and OPT by 74.4%.

Smartphone Software Development Course Design Based on Android

Mobile computing is popular when wireless network has been deployed almost everywhere. Smartphones have been the important tools in our society for the abundant functions including communication, entertainment and online office etc as the pivotal devices of mobile computing. Smartphone software development has also become more important than before. Android is one of the emerging leading operating systems for smartphones as an open source system platform. Many smartphones have adopted this platform and more smartphones will do so in the future. It is also an emerging problem on how to develop software for smartphones based on Android and those platforms like it. We propose smartphone software development course design based on Android in this paper. What this course focuses is how to teach the development technology to Students. The course design has two parts including the syllabus design and hands-on lab design. At the same time, the innovations are also described in detail and these innovations play a key role in the teaching.

Multicore Challenge in Pervasive Computing Education

With the progress of the semiconductor technology, multicore has been more and more important than before. In multicore architecture, more than one processor core is integrated onto one single chip to improve the performance. The processor technology has been greatly changed by this architecture. In pervasive computing, different multicore processors are provided to enhance the computing ability. And It is also an challenge to teach the students how to adapt to this architecture. In this paper, we present the multicore education for pervasive computing in universities of China. We depict the curricula design for multicore education. And the experiences in multicore education from the universities of China are also presented.

Exploring multicore computing education in China by model curriculum construction

Chip Multiprocessor (CMP) has been the main stream in microprocessor design with the progress in semiconductor technology area. It has brought new changes to computer architecture. This is also an enormous challenge to the universities in how to teach the new concepts to the students. We have designed an independent multicore curriculum in Zhejiang University to introduce multicore computing into our university. This curriculum has been identified as Model Curriculum in China. In this paper, we share our experiences in multicore education by model curriculum construction.

Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors

Dynamic voltage scaling (DVS) is an effective technique for reducing the energy consumption in embedded systems. There are several advantages using DVS technique into compiler framework. This paper present a framework for reducing energy consumption in embedded processors using the dynamic compiler collaborate with DVS technique. Two algorithms are implemented in this framework, and the framework is implemented using the Intel PIN systems and is deployed in a real hardware platform. Experimental results based on the software and hardware platform, show that significant energy saving are achieved while performance loss less than 5%.

The Practice of Remote Education on Information Security

With the rapid development of computer science, its education mode also changes a lot. Teaching and learning are not restricted by the physical distance with the help of the networking. Remote education becomes more popular because of its convenience and resource saving. Meanwhile, the network security is a hotspot in the world for the rapid and wide using of the network. In this paper, we share our experiences on a practice of information security theory curriculum based on the networking technology. We developed a remote education platform which has been used in our curriculum. The statistic results show that most students are quite satisfied with this remote education platform and show great learning effect on the information security theory curriculum.

Adapting Experiments of Embedded System Curriculum Designed Based on Embedded IA to Atom

As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our experiences in the experiment teaching of embedded system.

A Redundancy Mechanism under Single Chip Multiprocessor Architecture

Chip multiprocessor (CMP) will become more popular in embedded systems. As clock frequency increases, dependency among core blocks rises, which therefore tends to reduce performance of system and be more unstable. Redundancy is a way to improve the dependability of the system. But the traditional methods cannot make full use of the computing capacity of CMP. In this paper, we propose a new redundancy mechanism. The whole system is reorganized using lightweight virtualization. A group of processors and a block of memory are treated as a single logical computing unit each of which corresponds to a processer separately. In this way, only a distributor and an arbiter need to be added into operating system with least effort. The distributor dispatches one task to all the logical computing units. After execution, the arbiter gathers all results to analyze whether they are dependable. Because the distributor and the arbiter are very simple, total overhead of the system are very low. Experiment results show the proposed method is practical with average overhead less than 8%.

Teaching Reform of Information Security Curriculum of Distance Learning

Information security is becoming more and more important in recent years. It covers fruitful contents and still in rapid continuous changes. How to teach information security is a challenge to universities. Distance learning can provide a favorable environment to information security. An information security curriculum of distance learning has been designed in Zhejiang University. Distance learning curriculum has its own features and then it is different in curriculum design. In this paper, we will describe our curriculum design and share our experiences in teaching reform. In our curriculum, the teaching reform helps us boost our design and improve our teaching.

Load Balance Scheduling Algorithm for CMP Architecture

Chip MultiProcessor (CMP) has been the main stream in microprocessor design. Shared on-chip L2 caches are widely used in processors with homogeneous CMP architecture. In the paper, we propose a scheduling algorithm for such processors and the shared L2 caches are taken into account in this algorithm. First, the processor cores on chip will be divided into different core groups. The scheduling domain is also constructed according to these core groups. And then the load vectors for load balance are defined. Then a scheduling algorithm is designed and implemented for load balance on CMP architecture. We have compared our algorithm with the CMP scheduling algorithm of Linux. The experimental results show that, when there are multi-threads in execution, the load balancing between processors is achieved by our algorithm, the total execution time is reduced by 3%, and the miss rate of L2 cache is reduced by 0.2% as well.