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Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA

Reconfigurable computing based on FPGAs (Field Programmable Gate Arrays) has been a promising solution to improve the performance with high flexibility. However, the physical capacity limitation of FPGAs prevents its wide adoption in real world. In this paper, a homogeneous NoC-based FPGA architecture is proposed, in which reconfigurable and I/O resources are interconnected via NoC so that reconfigurable modules can be placed anywhere once enough space available. Meanwhile, a virtual FPGA is proposed with which over large circuit can be implemented on a limited capacity FPGA. The experiment verified that our approach can provide more flexible reconfiguration, and combing NOC on FPGA, the resource utilization increased within 44.7%-53.5% because of the fragment in CRs benefit from such kind of dynamic partial configuration.

Input-Driven Reconfiguration for Area and Performance Adaption of Reconfigurable Accelerators

Attaching a reconfigurable loop accelerator to a processor for improving the performance and the efficiency of the system, which can be further enhanced by unrolling the loop to change its parallelism in a better way, is a promising development. The more a loop is unrolled, the wider the reconfigurable area that is exposed. However, the utilization of a loop accelerator is highly linked with the input. Also, in some situations, one will be wasting area to overunroll the loop. With a focus on the area and the performance balance, this paper proposes a dynamically adaptive reconfigurable accelerator framework for the processor/RL architecture. In the framework, reconfiguration of the accelerator is driven by the input. An accelerator selection model is presented for selecting an accelerator at run time among the predefined input patterns. Also, with the help of a detailed illustration of a bzip2 case study, experimental results were provided for the feasibility of the approach, which showed that up to 69.21% reconfigurable area is saved at a cost of 2.63% performance slowdown in the best case.

A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit

It’s a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic is logically divided into Reconfigurable Processing Units (RPUs), which are coupled with General Purpose Cores (GPCs) as co-processors via a configurable full crossbar switch. And a RPU-Manager (RPU-M) is designed to manage the RPUs. To verify RMC, a simulation methodology based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the accuracy of the hardware function core. The experimental results of workloads 3-DES, AES and JPEG_ENC show a 2.34X average speedup over software implementation, while the data and control transfer overhead is acceptable.

Embedded hard real-time scheduling algorithm based on task's resource requirement

The embedded systems are resource limited systems and response time is commonly one of the most important requirements. In this paper, we present a real-time scheduling algorithm based on tasks resource requirements for embedded system. In embedded systems, the resources and tasks are restricted, especially in specific systems. The tasks can be divided into different sets according to their resource requirements. In the same set, specific scheduling algorithm can be selected to schedule the tasks according to the features of the set. Thus different sets can have different scheduling algorithms. Then the scheduling sequences can be calculated as preparation partly. It is more efficient for embedded specific system.

Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

Reconfigurable computing is a promising approach with both flexibility and efficiency for high performance computing. However, the overhead of run-time reconfiguration affects the performance severely. In the paper, we develop a simple and effective method to hide the latency of configuration by configuration prefetching at runtime. A simulation platform based on Simics is developed for evaluation. The experimental results show that the predictive accuracy is rather high, the hit rate of reconfigurable processing unit is increased by 24.6%∼53.7% when reconfigurable resource is not adequate.

Adapting Experiments of Embedded System Curriculum Designed Based on Embedded IA to Atom

As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our experiences in the experiment teaching of embedded system.

A Novel Architecture for Embedded Database Management System on Chip

As new applications of ubiquitous computing and ambient intelligence appear, there is great need to embed database technology into various lightweight computing devices. And the semiconductor industry allowing more and more transistors to be fabricated on a single silicon chip makes it possible to implement ever complex microelectronic system containing a CPU, embedded memory, I/O devices. In this paper, a novel architecture is proposed for a back-end embedded database management system on chip (DBoC) for lightweight computing devices. And in this architecture, a set of binary commands are defined as database management language (DBML) named DBML command, a hardware solution for DBML Command Interpreter and a data flow controller from information control unit of manticore are provided with.

The Implementation of a Mobile Java Debug Tool

As the handsets integrated the J2ME environment is increasing in recent time. After PhoneME which is one implementation of the J2ME had become an open project, transplanting it to many different platforms become a hotspot for some time. There are some implementations for the online debugging between the PC and specific embedded device. But there isn’t a well-designed architecture for the debugging processes between the PC and the mobile phone, there just some assistance tools for co-debug. As the mobile phone industry developing, there are many smart phones with affluent hardware resource. This makes the co-debug between PC and smart mobile phone become possible. In this paper, we present a debug framework for the JAVA application development platform across the PC and mobile phone. With this framework, we can develop the MIDlets for specific embedded device more convenient.

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

It’s a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated into RPUs logically, which are coupled with general purpose cores as co-processors via a full crossbar switch. An RPU Manager (RPU-M) is also designed to manage RPUs. To verify RMC, a simulation method based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the evaluation accuracy of hardware function cores. Five workloads are selected to test RMC, including 3-DES, AES, SHA2, IDCT and JPEG_ENC. The experimental results show a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable.

Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip

In recent years, special attention has been paid to slot-based reconfigurable devices interconnected by NoCs (networks on chip). An urgent problem is how one reallocatable task can communicate with others. This paper proposes two approaches to augment NoC for slot-based reconfigurable system by adding a naming module to solve this problem. In the first approach, the naming module is outside of the mesh and connects to each slot using a dedicated channel. In the second approach, the naming module is inside the mesh and communicates with other slots using NoC routing. As for the results, for the best situation in a 16x16 mesh, average delay increases by 1.15% and by 6.00% for over-network mode and in-network mode respectively. These two average delays would increase with increasing reconfiguration rate, with the increase for the in-network mode being faster than that for the over-network mode. And the decrease of throughput is negligible in both modes.