Degui Feng

The Implementation of a Mobile Java Debug Tool

As the handsets integrated the J2ME environment is increasing in recent time. After PhoneME which is one implementation of the J2ME had become an open project, transplanting it to many different platforms become a hotspot for some time. There are some implementations for the online debugging between the PC and specific embedded device. But there isn’t a well-designed architecture for the debugging processes between the PC and the mobile phone, there just some assistance tools for co-debug. As the mobile phone industry developing, there are many smart phones with affluent hardware resource. This makes the co-debug between PC and smart mobile phone become possible. In this paper, we present a debug framework for the JAVA application development platform across the PC and mobile phone. With this framework, we can develop the MIDlets for specific embedded device more convenient.

A Java Development Platform in Mobile System for Smart Home

With the development of embedded technology, smart home has been widely used to practice field. Due to the characteristics of cross-platform and faster development life cycle, Java becomes one of the most important language in the mobile application development. From the overall view of application development, this paper describes a Java-based application development platform (JADP) for the mobile system. Our platform¿s features include flexible remote debugger, rich APIs and service components, efficient deploy tool etc. Mobile device applications developers can now easily develop, optimize, deploy and verify their applications with our Java development platform.

Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip

In recent years, special attention has been paid to slot-based reconfigurable devices interconnected by NoCs (networks on chip). An urgent problem is how one reallocatable task can communicate with others. This paper proposes two approaches to augment NoC for slot-based reconfigurable system by adding a naming module to solve this problem. In the first approach, the naming module is outside of the mesh and connects to each slot using a dedicated channel. In the second approach, the naming module is inside the mesh and communicates with other slots using NoC routing. As for the results, for the best situation in a 16x16 mesh, average delay increases by 1.15% and by 6.00% for over-network mode and in-network mode respectively. These two average delays would increase with increasing reconfiguration rate, with the increase for the in-network mode being faster than that for the over-network mode. And the decrease of throughput is negligible in both modes.

The Design and Implementation of Adaptive Reconfigurable Computing Array

More and more reconfigurable devices have been used to accelerate specific computation in traditional computing systems. But isolate reconfigurable system has some shortcomings such as limited computation ability, low utilization of reconfigurable devices. In this paper, a networked adaptive array of reconfigurable computing nodes was proposed, which is composed of host and reconfigurable devices. Via sharing reconfigurable resources among nodes in the system, the ability of computation of one node is enhanced and the utilization ratio of reconfigurable resources is increased. The experiment result shows that about 19.5%-48.2% execution time could be reduced by using 2-5 nodes in the array comparing with a single node for heavy workload.

SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework

Chip multiprocessor (CMP) has been the mainstream of processor design with the progress in semiconductor technology. It provides higher concurrency for the threads compared with the traditional single-core processor. Lock-based synchronization of multi-threads has been proved as an inefficient approach with high overhead. The previous works show that TM is an efficient solution to solve the synchronization of multi-threads. This paper presents SPMTM, a novel on-chip memory based nested TM framework. The on-chip memory used in this framework is not cache but scratchpad memory (SPM), which is software-controlled SRAM on chip. TM information will be stored in SPM to enhance the access speed and reduce the power consumption in SPMTM. Experimental results show that SPMTM can obtain average 16.3% performance improvement of the benchmarks compared with lock-based synchronization and with the increase in the number of processor core, the performance improvement is more significant.