Qiqing C. Ouyang

Finfet circuits with various fin heights

FINFET DEVICE HAVING A MERGED SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME

REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME

Finfet device with vertical silicide on recessed source/drain epitaxy regions

SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL

FinFET DEVICE INCLUDING FINS HAVING A SMALLER THICKNESS IN A CHANNEL REGION, AND A METHOD OF MANUFACTURING SAME

SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

SEMICONDUCTOR DEVICE INCLUDING EPITAXIALLY FORMED BURIED CHANNEL REGION

REDUCED RESISTANCE SHORT-CHANNEL InGaAs PLANAR MOSFET