Keith E. Fogel

Kerf-Less Removal of Si, Ge, and III–V Layers by Controlled Spalling to Enable Low-Cost PV Technologies

Kerf-less removal of surface layers of photovoltaic materials including silicon, germanium, and III-Vs is demonstrated by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material, and the controlled removal of a continuous surface layer could be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer. Because the entire process is at room temperature, this technique can be applied to kerf-free ingot dicing, removal of preformed p-n junctions or epitaxial layers, or even completed devices. We successfully demonstrate kerf-free ingot dicing, as well as the removal of III-V single-junction epitaxial layers from a Ge substrate. Solar cells formed on the spalled and transferred single-junction layers showed similar characteristics to nonspalled (bulk) cells, indicating that the quality of the epitaxial layers is not compromised as a result of spalling.

High-Performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

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Monolayer Graphene via Two Transfers Oriented monolayers of graphene containing some bilayer regions can be formed on silicon carbide crystal surfaces, but, to be cost effective, the graphene needs to be exfoliated and transferred to other substrates so that the silicon carbide crystal can be reused. Kim et al. (p. 833, published online 31 October) used a nickel film grown to a thickness designed to impart a particular surface stress as a “handle” to exfoliate the graphene layer for transfer to a silica substrate. An additional gold layer was then used to remove the excess monolayer from the bilayer regions to create a monolayer suitable for electronics applications. A two-step exfoliation process allows multiple transfers of oriented monolayer graphene from a silicon carbide surface. The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

-Channel MOSFETs With High-

In this letter, we demonstrate the effectiveness of the controlled spalling technology for producing high-efficiency (28.7%) thin-film InGaP/(In)GaAs/Ge tandem solar cells. The controlled spalling technique was employed to separate the as-grown solar cell structure from the host Ge wafer followed by its transfer to an arbitrary Si support substrate. The structural and electrical properties of the thin-film tandem cells were examined and compared against those on the original bulk Ge substrate. The comparison of the electrical data suggests the equivalency in cell parameters for both the thin-film (spalled) and bulk (non-spalled) cells, confirming that the controlled spalling technology does maintain the integrity of all layers in such an elaborate solar cell structure.

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We demonstrate that the crystal orientation of single-crystal silicon layers may be changed in selected areas from one orientation to another by an amorphization/templated recrystallization (ATR) process, and then introduce ATR as an alternative approach for fabricating planar hybrid orientation substrates with surface regions of (100)- and (110)-oriented Si. The ATR technique, applied to a starting substrate comprising a thin (50–200 nm) overlayer of (100) or (110) Si on a (110) or (100) Si handle wafer, consists of two process steps: (i) Si+ or Ge+ ion implantation to create an amorphous silicon (a-Si) layer extending from the top of the overlayer to a depth below the overlayer/handle wafer interface, and (ii) a thermal anneal to produce the handle-wafer-templated epitaxial recrystallization of the a-Si layer. Regions exposed to the ATR process assume the orientation of the handle wafer while regions not exposed to the ATR process retain their original orientation. The practicality of this approach is d...

Gate Dielectrics and

The hole transport characteristics in partially strained (0.5%) Ge p-channel MOSFETs formed on silicon-germanium-on-insulator (SGOI) substrates were investigated for gate lengths down to 65 nm. We demonstrate that high hole mobility is maintained down to the shortest channel lengths. The channel conductance from these devices is measured and compared to state-of-the-art high-performance Si channel P-MOSFETs.

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In this communication, we present what may be the simplest method yet devised for removing surface layers from brittle substrates. The process is called controlled spalling technology (CST) and works by depositing a tensile stressor layer on the surface of a substrate, introducing a crack near the edge of the substrate, and mechanically guiding the crack as a single fracture front across the surface. The entire process is performed at room-temperature using only common laboratory equipment. We present here, for the first time, the specific process conditions required for controlled spalling of Ge 〈0 0 1〉 substrates using Ni as the stressor layer. We also illustrate the versatility of CST by removing completed CMOS circuits from a Si wafer and demonstrate functionality of the flexible circuits. Raman spectroscopy of spalled circuits with the Ni stressor intact indicates a residual compressive Si strain of 0.0029, in good agreement with the calculated value of 0.0022. Therefore, CST also permits new opportunities for strain engineering of nanoscale devices.

-Si Passivation

Trench-edge defects formed during epitaxial recrystallization of trench-bounded amorphized silicon (a-Si) regions are examined as a function of Si substrate crystal orientation. In Si (001), rectilinear a-Si features having edges aligned with the crystal’s in-plane ⟨110⟩ directions recrystallize leaving trench-edge defects along all trench edges, whereas the identical features in Si (011) recrystallize without trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨100⟩ direction and with trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨110⟩ direction. The positions and lateral extent of these trench-edge defects suggest that their source is defective epitaxy on slow-growing {111} planes formed during recrystallization. A heuristic model proposed to explain the formation of these {111} planes correctly predicts the essentially defect-free recrystallization seen for rectilinear a-Si features in Si (001) having edges aligned with the crystal’s in-plane ⟨100⟩ dire...

Layer-Resolved Graphene Transfer via Engineered Strain Layers

Elasticon connectors have been developed for a wide variety of interconnection and test applications which include module-to-board, board-to-board interconnections; high density module, board and LCD testings; as well as chip/wafer testing and burn-in to produce Known-Good-Die. Depending on the applications, the Elasticon connectors can be fabricated into two basic types, the single-sided (integrated to a substrate) and the double-sided (interposer) structure. The single-sided structure, the Integrated Probe, is designed and fabricated for test and burn-in applications. The density, compliance, thickness, pattern and size of both the one- and two-sided structures can be easily tailored to meet the requirements of each specific application. The fabrication processes involve wire bonding, laser and polymer casting and curing. The electrical, mechanical and thermal properties of the connector have been fully characterized. To achieve high compliance with low contact force, a proprietary elastomeric material has been formulated to achieve not only high compliance but high thermal stability. The conductive element uses highly conductive, corrosion free, and oxidation resistant noble metals and their alloys. The reliability and durability of the elastomeric connector have been evaluated with mechanical cycling, thermal cycling, stress relaxation, outgassing, and temperature and humidity rest. The thermal stability of the connector, including both the polymer and the conductive element, has been measured to exceed the burn-in temperatures, which range from 125 to 180/spl deg/C.

High-efficiency thin-film InGaP/InGaAs/Ge tandem solar cells enabled by controlled spalling technology

The shapes of the recrystallization fronts observed during solid phase epitaxy (SPE) in line-shaped amorphized Si (a-Si) regions in single-crystal (001) and (011) Si are shown to exhibit a complex time evolution inconsistent with simple models in which regrowth behavior is determined exclusively by the competition between fixed-growth-rate lateral and vertical SPE. We find that the main features of our data for ⟨110⟩-aligned a-Si lines may be explained by the propensity of the lateral and vertical growth fronts to form stable a-Si∕{111} interfaces at their edges. These same a-Si∕{111} interfaces have been previously implicated as the root cause of the trench-edge defects produced during the recrystallization of patterned a-Si regions bounded laterally by oxide-filled trenches. An extension of a nanofacet model recently developed to explain the trench-edge defects is shown to explain many of the observed recrystallization behaviors.