Pranita Kerber

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- VT FinFETs makes them suitable for memory cell applications.

Strained SOI FINFET SRAM Design

Impact of strained silicon effects in double-gated FinFET structures on static random access memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) SRAM cell embodiments representing unstrained, strained, and NFET-only-strained devices are compared against a planar PDSOI SRAM cell design. The metrics encompass both static and dynamic behavior of the cell and are analyzed through 2-D process hardware-calibrated device models (Lg=25 nm). The key findings of this letter are: 1) PFET devices with tensile strain are found to degrade the FinFET cell Read Noise Margin and cell ability to write a strong “1”; 2) by restricting the tensile strain to the NFET devices FinFET SRAM cell Read stability and access times improve by 10%-20% relative to their unstrained FinFET and NFET-only strained PDSOI counterparts.

A Simulation Study of Oxygen Vacancy-Induced Variability in

Deposition of a metal gate on high-K dielectric HfO2 is known to generate oxygen vacancy (OVs) defects. Positively charged OVs in the dielectric affect the gate electrostatics and modulate the effective gate workfunction (WF). Count and spatial allocation of OVs varies from device-to-device and induces significant local variability in WF and Vth. This paper presents the statistical models to simulate OV concentration and placement depending on the gate formation conditions. OV-induced variability is studied for SOI FinFET, and compared against the other sources of variability across the technologies. The implications of gate first and gate last processes to the OV concentration/distribution are studied. Simulations show that with channel length and gate dielectric thickness scaling, the OV-induced variability becomes a significant concern.

{\rm HfO}_{2}

We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.

/Metal Gated SOI FinFET

This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current technologies implement airgaps only at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

Channel thickness Tch dependence of electron mobility μκρρ in thin In<inf>0.53</inf>Ga<inf>0.47</inf>As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed I<inf>D</inf>-measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations of μκρρ due to charge trapping with slow/parametric measurements. Furthermore, annealing is demonstrated to strongly suppress charge trapping, which results in μ<inf>κρρ</inf> = 1015 cm²/Vs at T<inf>ch</inf> = 7.1 nm, carrier density Ns = 3 × 10¹² cm⁻², and T = 300 K. We demonstrate that room-temperature μκρρ degrades by less than 10% as T<inf>ch</inf> is scaled from 300 nm down to 7 nm, thus indicating that there is no “mobility bottleneck” down to T<inf>ch</inf> = 7 nm.

Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits

Quick calculation of capacitance without field solver simulations is desirable to evaluate process assumptions and predict interconnect performance with minimal computation time. At sub-10 nm technology nodes complex interconnect stacks and shrinking dimensions preclude the use of empirical formulae. Here, we extend a physically based quick capacitance model to incorporate sub-10-nm technology elements such as damage layers, multilayer dielectric caps and non-rectangular interconnect cross-sections. The computation time of our model, implemented in standard spreadsheet software is negligible and validation with actual 10-nm node interconnect dimensions shows <;1% error to field solver results. Our model also demonstrates good sensitivity to key process parameters. Our results would be useful to enable quick capacitance estimations for technology and process design.

Electron mobility in thin In 0.53 Ga 0.47 As channel

The net charge state was probed of metal-oxide-semiconductor gate stacks consisting of In0.53Ga0.47As /high-κ dielectric/5 nm TiN, for both Al2O3 and HfO2 dielectrics, via investigation of band bending at the InGaAs/high-κ interface. Using pump-probe photoelectron spectroscopy, changes to band bending were studied for each sequential layer deposited onto the InGaAs substrate and subsequent annealing up to 600 °C. Two behavioral regions were observed in annealing studies: (1) a lower temperature ( 350 °C), associated with a net positive charge increase within the oxide. These band bending measurements delineate the impact of processing steps inherently inaccessible via capacitance-voltage electrical characterization.