Qiuyun Xu

High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits

We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technologys 10-kA/cm2 Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single- precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.

Design of an Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic

We designed and implemented an extremely energy- efficient hardware algorithm using adiabatic quantum- flux-parametron (AQFP) logic based on a hardware- algorithm known as the Collatz conjecture. The circuit is composed of mergers, odd- even check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapid-single-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation With HDL Back-End Verification

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient platform to perform computing with superconductivity. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using ac excitation currents. During the past few years, the AQFP logic family has been investigated and implemented into various operational circuits. Experimental results prove the robustness of building large-scale integrated AQFP circuits. In this paper, an AQFP very large scale integration (VLSI) design flow is introduced and detailed with a 16-b decoder as an example circuit. By including logic synthesis and automatic routing tools, this AQFP VLSI design flow is capable of converting a high-level description of a system into a physical layout. Analysis suggests that a reduction of more than 40% in circuit area and a much higher design efficiency can be obtained, compared to a previous design done manually.

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

Adiabatic quantum-flux-parametron (AQFP) circuits are currently verified by analog-based simulation, which would be an obstacle for large-scale circuits design. In this paper, we present a logic simulation model for AQFP logic. We made a functional model based on a finite-state machine approach using a hardware description language, which enables the simulation of large-scale AQFP circuits using commercially available logic simulation tools. We have developed a library for logic simulation and implemented an 8-bit carry look-ahead adder, which is composed of over 1000 Josephson junctions. We also include timing information in our logic simulation models for timing analysis. Since the library is based on a parameterized approach, it can be easily modified for different fabrication technologies and low-level circuit parameters.

Analysis of computational energy efficiency in single-flux-quantum electronics by implementing an integer-based hardware-algorithm

We designed and implemented a single-flux-quantum (SFQ) based hardware-algorithm known as the 3n+1 conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator and a central processor. This design can perform with a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW based on the AIST 10 kA/cm2 advanced Nb process. The power consumption was further reduced by using an LR-biasing approach.

Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration Algorithms

The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of “1.” The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm2 advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 107 numbers every second with an energy efficiency of about 5 × 1010 numbers per Joule.