Christopher L. Ayala

Design of an Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic

We designed and implemented an extremely energy- efficient hardware algorithm using adiabatic quantum- flux-parametron (AQFP) logic based on a hardware- algorithm known as the Collatz conjecture. The circuit is composed of mergers, odd- even check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapid-single-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation With HDL Back-End Verification

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient platform to perform computing with superconductivity. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using ac excitation currents. During the past few years, the AQFP logic family has been investigated and implemented into various operational circuits. Experimental results prove the robustness of building large-scale integrated AQFP circuits. In this paper, an AQFP very large scale integration (VLSI) design flow is introduced and detailed with a 16-b decoder as an example circuit. By including logic synthesis and automatic routing tools, this AQFP VLSI design flow is capable of converting a high-level description of a system into a physical layout. Analysis suggests that a reduction of more than 40% in circuit area and a much higher design efficiency can be obtained, compared to a previous design done manually.

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

Adiabatic quantum-flux-parametron (AQFP) circuits are currently verified by analog-based simulation, which would be an obstacle for large-scale circuits design. In this paper, we present a logic simulation model for AQFP logic. We made a functional model based on a finite-state machine approach using a hardware description language, which enables the simulation of large-scale AQFP circuits using commercially available logic simulation tools. We have developed a library for logic simulation and implemented an 8-bit carry look-ahead adder, which is composed of over 1000 Josephson junctions. We also include timing information in our logic simulation models for timing analysis. Since the library is based on a parameterized approach, it can be easily modified for different fabrication technologies and low-level circuit parameters.

Development and Demonstration of Routing and Placement EDA Tools for Large-Scale Adiabatic Quantum-Flux-Parametron Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient superconductor logic due to zero static power dissipation and adiabatic switching operation. However, there is a shortage of electronic design automation (EDA) software tools adaptable to AQFP logic. Such tools are essential for designing large-scale-integration circuits efficiently. Therefore, we have developed a first set of EDA tools that handle cell placement and wiring, written in SKILL, the Cadence scripting language. Our tools also consider the maximum wire length constraint that exists in AQFP logic. First, AQFP logic cells are repositioned via the genetic algorithm to minimize the number of wires that violate the wiring length constraint. Buffers are then automatically inserted as signal repeaters for logic rows where the violations still exist. We then complete the logic wiring of the circuit using the channel routing algorithm. We demonstrate the usability of the EDA tools by designing a 16-bit adder as well as a randomly generated test circuit.