Quazi Deen Mohd Khosru

NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability

Extremely thin (equivalent oxide thickness, Teq=1.2 nm) silicon-nitride high-k (er=7.2) gate dielectrics have been formed at low temperatures (⩽550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.

Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics

An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

Abstract An extremely thin (∼2 monolayers) silicon nitride layer has been deposited on thermally grown SiO 2 by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness ( T eq =2.2 nm) efficiently reduce the boron diffusion from p + poly-Si gate without the pile up of nitrogen atoms at the SiO 2 /Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO 2 especially in the thin ( An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO 2 stack gate dielectrics compared with those of conventional SiO 2 dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO 2 and SiO 2 /Si-substrate interfaces for the SiO 2 gate dielectrics and only near the SiO 2 /Si-substrate interface for the stack gate dielectrics. Employing annealing in NH 3 at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO 2 , further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH 3 annealing. Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.

Spatial distribution of trapped holes in the oxide of metal oxide semiconductor field-effect transistors after uniform hot-hole injection

Hole trap distribution and time dependence of the charge-free layer in the gate-oxide of p-channel metal oxide semiconductor (pMOS) transistors have been investigated after uniform hot-hole injection into the oxide of a set of pMOS transistors having very thin oxide thicknesses in the range of 4.6 to 10.6 nm. It has been found that the trap distribution has an exponential variation with respect to the distance from the Si/SiO2 interface and exists within 6 nm from the interface. A slight dependence of trapped-hole density on the oxide electric field was also found. A charge-free layer exists near the interface as a consequence of hole detrapping during relaxation. Measured time dependence of the charge-free layer during relaxation reveals that it increases initially with time and saturates at around 4 nm.

Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal–oxide–semiconductor structures

A simple and effective method for the extraction of interface trap distribution in ultrathin metal–oxide–semiconductor (MOS) structures is presented. By a critical analysis of bipolar-pulse-induced currents through MOS capacitors, a technique is developed to determine the energy distribution of the interface traps without requiring the knowledge of surface potential and doping profile in the semiconductor. The proposed technique can be efficiently used to probe electrical stress, hot-carrier, and radiation-induced interfacial degradations in ultrathin MOS structures.

Low thermal-budget ultrathin NH/sub 3/-annealed atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics with excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics annealed in NH/sub 3/ at a moderate temperature of 550/spl deg/C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO/sub 2/ stack dielectrics without NH/sub 3/-annealing and conventional thermal SiO/sub 2/ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices.

Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectrics for advanced complementary metal–oxide–semiconductor technology

We report a high-quality, ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectric. p+-polycrystalline silicon gate metal–oxide–semiconductor (MOS) capacitors with the proposed dielectrics showed enhanced reliability with respect to conventional SiO2. An exciting feature of suppressed soft-breakdown (SBD) events is observed in ramped voltage stressing which has been reconfirmed during time-dependent-dielectric breakdown measurements under constant field stressing. Introducing the idea of injected-carrier-induced localized physical damages resulting in the formation of conductive filaments near both Si/SiO2 and poly-Si/SiO2 interfaces, a model has been proposed to explain the SBD phenomena observed in the conventional SiO2 dielectrics. It is then consistently extended to explain the suppressed SBD in the proposed dielectrics. The reported dielectric can be a good choice to meet the urgent need for highly reliable ultrathin gate dielectrics in nanoscale complementary-MOS technology.

Hot-Hole-Induced Interface State Generation in p-Channel MOSFETs with Thin Gate Oxide

Interface state generation in p-channel metal oxide semiconductor field effect transistors (MOSFETs) due to uniform hot-hole injection into the thin gate oxide and postinjection behavior of the generated interface states are investigated. The absence of a significant oxide electric field dependence of interface state generation supports the existence of a single generation mechanism. The experimental results suggest a mechanism associated with the interaction of neutral hydrogen for interface state generation. The number of generated interface states is linearly proportional to the number of trapped holes regardless of oxide thickness, which indicates active involvement of hole trapping in the formation of interface states. In contrast to the reports describing time-delayed formation of interface states during relaxation, we observed spontaneous postinjection annihilation of the generated interface states which was also linearly related to the number of detrapped holes. The experimental results suggest the presence of a reversible atomic structure at the Si/SiO2 interface with respect to trapping and subsequent detrapping of holes. The annealing efficiency of the generated interface states depends on the postinjection oxide field polarity.

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO 2 stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.

Low-temperature formation of highly reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal–oxide–semiconductor technology

Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride was deposited on Si substrates by atomic-layer deposition (ALD) at low temperatures (<550 °C). Substantial enhancement of reliability was obtained with respect to the conventional SiO2 samples. An exciting feature of suppressed soft breakdown events was observed. Injected-carrier-induced physical damage, which results in the formation of the conductive filaments at the poly-Si/ALD-Si-nitride and ALD-Si-nitride/Si-substrate interfaces, is suppressed due to the higher stability of the Si–N bonds than that of the strained Si–O bonds. This suppression of physical damage leads to enhanced reliability. Therefore, the ALD silicon nitride can be a good choice for a highly reliable ultrathin gate dielectric in deep submicron complementary metal–oxide–semiconductor technology.