Toshirou Kidera

NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability

Extremely thin (equivalent oxide thickness, Teq=1.2 nm) silicon-nitride high-k (er=7.2) gate dielectrics have been formed at low temperatures (⩽550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.

Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition

Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride layers were deposited on Si substrates by an atomic-layer-deposition (ALD) technique at low temperatures (<550 °C). The interface state density at the ALD silicon nitride/Si-substrate interface was almost the same as that of the gate SiO2. No hysteresis was observed in the gate capacitance–gate voltage characteristics. The gate leakage current was the level comparable with that through SiO2 of the same Teq. The conduction mechanism of the leakage current was investigated and was found to be the direct tunneling. The ALD technique allows us to fabricate an extremely thin, very uniform silicon nitride layer with atomic-scale control for the near-future gate dielectrics.

Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics

An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.

Coulomb blockade effects and conduction mechanism in extremely thin polycrystalline-silicon wires

Narrow (⩾95 nm) and extremely thin (∼7 nm) heavily phosphorous-doped polycrystalline-silicon (poly-Si) wires were fabricated by low-pressure chemical vapor deposition. The electrical conduction mechanism has been investigated at low temperatures (down to ∼5 K), and observation by transmission electron microscopy (TEM) was carried out. Single-electron effects such as Coulomb oscillations have been observed at temperatures up to 80 K. The size of the island in the poly-Si wires was estimated from the electrical properties, and it was in the same order as the grain size of the poly-Si measured by TEM. A maximum tunnel barrier height of ∼26 meV of the poly-Si grain boundary is obtained from the temperature dependence of the conductance of the sample. A model for the electronic conduction through multiple islands was proposed from the width dependence of their electrical properties.

Characterization of atomic-layer-deposited silicon nitride/SiO2 stacked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors

An extremely thin (∼0.4 nm) silicon nitride layer has been deposited on thermally grown SiO2 by an atomic-layer-deposition (ALD) technique. The ALD silicon nitride is thermally stable as confirmed by x-ray photoelectron spectroscopy. The surface microroughness measured using atomic force microscopy is extremely small (average surface microroughness Ra of 0.031 nm) for the ALD silicon nitride on SiO2, especially in the thin thickness region (<0.5 nm). A smooth interface between the ALD silicon nitride and the poly-Si gate was also confirmed by transmission electron microscopy. The ALD technique allows us to fabricate an extremely thin, very uniform silicon nitride layer with atomic scale control. The boron penetration through the stacked gate dielectrics has dramatically been suppressed, and the reliability of the metal-oxide-semiconductor diodes with the stacked gate dielectrics has been significantly improved as confirmed by capacitance–voltage, gate current–gate voltage, and time-dependent dielectric-br...

Low-temperature formation of highly reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal–oxide–semiconductor technology

Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride was deposited on Si substrates by atomic-layer deposition (ALD) at low temperatures (<550 °C). Substantial enhancement of reliability was obtained with respect to the conventional SiO2 samples. An exciting feature of suppressed soft breakdown events was observed. Injected-carrier-induced physical damage, which results in the formation of the conductive filaments at the poly-Si/ALD-Si-nitride and ALD-Si-nitride/Si-substrate interfaces, is suppressed due to the higher stability of the Si–N bonds than that of the strained Si–O bonds. This suppression of physical damage leads to enhanced reliability. Therefore, the ALD silicon nitride can be a good choice for a highly reliable ultrathin gate dielectric in deep submicron complementary metal–oxide–semiconductor technology.

Field-Shield Trench Isolation with Self-Aligned Field Oxide

A novel fabrication technique for submicrometer trench isolation is proposed. This features a phosphorus-doped polysilicon field shield filled into the trench and a thick isolation oxide formed on polysilicon by impurity-enhanced oxidation (IEO). Due to the oxide entirely covering the trench shoulder by a self-aligned process, the proposed structure has notable merits: (i) the anomalous hump current in Id-Vg subthreshold characteristics is suppressed even in a narrow-channel transistor and (ii) the proposed structure provides less susceptibility to crystal defect generation. These can facilitate fabrication of controllable devices. In addition, a deeply implanted channel stopper yields a low parasitic capacitance for fast device operation and excellent isolation performance characteristics such as low field penetration and low punch-through current. These are attributed to the effect of the electric field shield.