Quentin P. Herr

Ultra-low-power superconductor logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses ac power carried on a transmission line, which also serves as a clock. Using simple experiments, we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins, and a low bit-error rate. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of single-flux-quantum signals with the design methodology of semiconductor digital logic, including low static power dissipation, low latency combinational logic, and efficient device count.

High speed data link between digital superconductor chips

Superconductor digital devices using single-flux-quantum (SFQ) data encoding offer higher speed at lower power than any other integrated circuit technology. For this very reason, interconnect is challenging. We report SFQ data transfer between chips flip chip mounted on a passive microstrip carrier. The flip-chip structure achieves bandwidths greater than 250 GHz. Unlike previous designs, our signal lines are terminated at both ends; this is accomplished using a driver that produces a double-flux-quantum signal. We measured the circuit for pseudorandom data in the range of 10–60 Gb/s. Bit error rates are measured down to 1E−10 and extrapolate to negligible values. The signal power on the microstrip is only 30 nW at 60 Gb ps.

Tools for the computer-aided design of multigigahertz superconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented.

A high density 4 kA/cm/sup 2/ Nb integrated circuit process

We have developed an improved 4 kA/cm/sup 2/ process technology that allows a significant increase in circuit speed and density. Improved photoresist and dry etch processes have reduced critical dimension (CD) variation and improved CD linearity to below 1 /spl mu/m. These improvements have enabled a substantial reduction in feature size and full utilization of existing photolithography and etch tools. We have demonstrated mire pitch of 2.0 /spl mu/m with less than 0.1 /spl mu/m CD loss. Minimum junction diameter and contact are 1.75 /spl mu/m and 1.0 /spl mu/m, respectively. Junctions, fabricated using a new barrier oxidation method with improved pressure control, have excellent I-V characteristics and array I/sub c/ nonuniformity less than 1.6% (1/spl sigma/). We have demonstrated a 200 GHz, 12-stage divider circuit that is the fastest complex digital superconductor integrated circuit fabricated to date. With the present process tools, defects are the limiting factor to further increases in circuit density and yield. In this paper, we discuss process improvements, electrical performance, defect reduction, and circuit performance.

Error rate of a superconducting circuit

The bit‐error rate of the Josephson junction single‐flux‐quantum comparator was measured as a function of bias current offset, at clock rates up to 10 GHz. The bit‐error rate versus offset is a smooth curve, measured over 16 decades of incidence, which linearly extrapolates to 10−49 for optimal bias. The lowest rate actually measured was 5×10−17, corresponding to 4 errors counted in 130 h.

Manufacturability of superconductor electronics for a petaflops-scale computer

Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling near-term technology solution for petaflops-scale computers. The proposed Hybrid Technology Multi-threaded (HTMT) petaflops computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Petabits/s. Due to fundamental time-of-flight and power dissipation limitations of semiconductor ICs, superconductor ICs at an integration level of 100 k gates/cm/sup 2/ are proposed for the HTMT computation modules. In this paper, we discuss the manufacturability of superconductor-based computation modules, including the IC foundry process, packaging, and data link out of the cryopackage. We focus on the critical technical challenges that exist in each of these areas and present a technology roadmap to achieve the HTMT requirements.

High speed testing of a four-bit RSFQ decimation digital filter

We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits.

Design and low speed testing of a four-bit RSFQ multiplier-accumulator

We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.

An 8-bit carry look-ahead adder with 150 ps latency and sub-microwatt power dissipation at 10 GHz

Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz.

Temperature-dependent bit-error rate of a clocked superconducting digital circuit

We measured the bit-error rate (BER) of an RS latch, a clocked SFQ circuit. A digital error-detection circuit was used to detect BER in the range unity to 10/sup -13/; below 10/sup -7/, the circuit was operated with a 12 GHz on-chip clock. BER was measured as a function of control current; both positive and negative control current was applied, leading to two distinct modes of error incidence. The error function curves extrapolate to 10/sup -80/ for optimal control current at a temperature of 5.5 K. Measurements were repeated over the range 3-7 K. Comparison to theoretical error-function estimates of BER indicate that the noise is strictly thermal.