Mark W. Johnson

Differential SFQ transmission using either inductive or capacitive coupling

The bias current requirement for RSFQ circuits is about an ampere per thousand gates. High current increases the thermal load of cables into the cryostat, produces undesirable currents and fields on-chip, and makes efficient power supply difficult. Series-biasing has been proposed, whereby the circuit is divided into blocks powered in series. This requires floating ground planes for each block, and differential signal propagation across ground plane boundaries where the blocks communicate. We have demonstrated transmission of pseudo-random data across a differential link using two distinct approaches, based on magnetic and capacitive coupling. For each circuit, we have measured data rates up to 30 Gb/s and bit error rates down to 10/sup -10/. Bit error rates extrapolate to lower values. Inductive coupling was implemented in TRWs 4 kA/cm/sup 2/ Nb process, capacitive coupling in TRWs 8 kA/cm/sup 2/ process.

Wide bandwidth oscillator/counter A/D converter

We present theory and performance data on oscillator/counter A/D converters fabricated in TRWs Nb process. Circuits with junction critical current density of 2 kA/cm/sup 2/ are discussed. This simple, low power A/D converter architecture is uniquely enabled by the wide bandwidth voltage-controlled oscillator (VCO) and compatible, ultra-fast superconductor single-flux-quantum (SFQ) divide-by-two flip-flops. The measured signal-to-noise ratio (SNR), frequency response, and signal distortion are discussed within the framework of a basic theory of performance as well as time-domain simulations. Noise contributions from quantization error, aperture jitter, and thermal noise are included. The measured signal-to-noise ratio (SNR) is shown to be within a few dB of theoretical performance over more than two decades of frequency. The frequency response is shown to fit well to the expected function through 1 GHz of signal frequency. Harmonic distortion is shown to be consistent with the non-linearity in the front-ends DC I-V characteristic which is subject to design improvement. This architecture extends to higher performance using a multi-junction VCO. Measured two-junction VCO SNR shows essentially the theoretical improvement over that of a single junction.

NbN circuits and packaging for 10 Kelvin IR focal plane array sensor signal processing

Infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 Kelvin, are presented. An ADC chip and digital signal processing chip are mounted on a 1.25 inch multi-chip module (MCM) with high bandwidth, low impedance interconnect. The populated MCM is designed to be installed into a module housing for operation with the cryogenic IR FPA. The 12-bit NbN SFQ counting ADC, previously used in a single chip version of the IR focal plane array sensor test system, is now implemented in an improved NbN process which includes a ground plane. Considerable attention has been focused on reducing parasitic inductance to compensate for the high characteristic inductance of the NbN films. These design improvements increase operating margins and circuit yield and make the ADC more robust in the presence of external system noise. Data from a bit-serial subtraction circuit to be used for pixel-by-pixel background subtraction is also presented. Finally, the design and electrical qualification of the physical package is described.

Monte-Carlo yield analysis [of Josephson circuits]

Speed, integration scale, and production cost of digital electronics are all constrained by circuit yield. This is true in any technology, In Josephson circuits, parameter variations figure prominently into the yield equation. Extensive statistical data exist for processes such as TRWs Nb and NbN technologies; yield calculation is a way to relate these data to circuit performance. To determine parametric yield using Monte Carlo, any and all circuit parameters are treated as Gaussian random variables. This kind of yield calculation has now been incorporated into the MALT optimization utility. As a worked example, we analyze a stacked SQUID amplifier design. The technique reveals circuit dynamics that are difficult to uncover by other means.

NbN and Nb SFQ device performance

The static frequency divider is commonly used as a performance benchmark for both superconductor and semiconductor digital device technologies. We present results of a static divide-by-two circuit, an NbN (1 kA/cm/sup 2/) SFQ T-flip-flop (TFF) operating to 97 GHz. Details of the measurement and operating criterion are discussed. Measurements of junction capacitance, a particularly important factor effecting device performance, are presented for TRWs NbN process. Simulations of expected device performance are shown to explain measured performance reasonably well. NbN results are presented alongside a those of a recent 8kA/cm/sup 2/ Nb divider operating at 300 GHz, as well as published Nb TFF results.

α–β crossover in glass formers as a function of molecular architecture

Abstract We present an experimental investigation of the relaxational processes related to the glass transition in several glass formers with more or less complex molecular architecture.The merging or crossing of the α and the β slow processes is discussed as a function of the molecular complexity.