Quoc-Tai Duong

Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering

In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend

A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 – 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 < −14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

Blocker and image reject low-IF frontend

In this paper we present a design of a low-IF receiver frontend using a selective N-path filter which serves blocker rejection, image rejection, and downconversion. The filter makes use of quadrature impedance upconversion technique using multiphase clocking and can be programmed by baseband capacitance and gm-cell transconductance values to meet the low-IF criterion in various cases. Presented is both a mathematical model of the filter and circuit simulation results including parasitic effects. Image rejection of 14 dB at IF that is provided by the filter mitigates the demands for the ultimate image rejection by the IQ mode. The blocker rejection at IF is larger than 50 dB. Designed in in 65 nm CMOS the low-IF receiver frontend with a modified N-path filter in simulations achieves NF <; 6 dB and OOB IIP3 > +8 dBm in 0.5-1 GHz band.

Wideband RF detector design for high performance on-chip test

A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

Low noise linear and wideband transconductance amplifier design for current-mode frontend

A low-noise transconductance amplifier (LNTA) aimed at current-mode (Saw-less, Software-define radio) wideband receiver frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient G<;sub>m<;/sub> gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65 nm CMOS, achieves in simulation the noise figure in range [1-1.34] dB and linearity of maximum IIP3 = 16.5 dBm over 0.5-6 GHz band. The maximum transconductance G<;sub>m<;/sub> = 12.9 mS, the return loss S11 <; -10 dB while the total power consumption is 4 mW for 1.2 V supply.

Highly linear open-loop output driver design for high speed capacitive DACs

Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

Focused calibration for advanced RF test with embedded RF detectors

In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

Power analysis for two-stage high resolution pipeline SAR ADC

In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

A 0.35μm CMOS 6-bit current steering DAC

This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm2 chip area in standard 0.35 μm Complementary metal-oxide-semiconductor (CMOS) technology. A spurious-free dynamic range (SFDR) of 25 dB has been measured over the complete Nyquist interval at sampling frequencies up to 800 MS/s with a power consumption of 165 mW at 3.3 V power supply.